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Galois fields are essential blocks of building many of cryptographic schemes. The main advantage of applying Galois fields over cryptographic applications are to reduce cost and increase the sufficiency of the performance. In past, they were interested in implement Galois field of characteristic 2 in most of the crypto-system application, but in the meantime, the researcher started to work on Galois field of odd characteristics which it has applications in many areas like Elliptic Curve Cryptography, Identity-based Encryption, Short Signature Schemes and etc. In this thesis, an odd characteristic Galois field was implemented. In particular, this thesis focuses on implementation of multiplication and reduction on GF(3m). Overview about the thesis idea was presented in the beginning. Finite field arithmetic was discussed where it shows some of the Galois fields important definitions and properties. In addition, irreducible polynomials over GF(p) where p is prime and the basic additional and multiplication over GF(pm) was discussed as well. Introduction to the proposed implementation started with the arithmetic of the Galois field characteristics 3. The problem formulation introduced by its mathematical representation and the Progressive Product Reduction (PPR) technique which is the technique used in this thesis. Implement three different semi-systolic arrays architecture with different projection functions. This stage followed by modeling assumption for complexity analysis for both area and delay where it used to compare proposed designs with other published designs. Proposed design gets verified by Matlab code implementation at the end of this thesis. / Graduate / Kareem.moeen@gmail.com

This thesis studies social influence from the perspective of users' characteristics. The importance of users' characteristics in word-of-mouth applications has been emphasized in economics and marketing fields. We model a category of users called mavens where their unique characteristics nominate them to be the preferable seeds in viral marketing applications. In addition, we develop some methods to learn their characteristics based on a real dataset. We also illustrate the ways to maximize information flow through mavens in social networks. Our experiments show that our model can successfully detect mavens as well as fulfill significant roles in maximizing the information flow in a social network where mavens considerably outperform general influential users for influence maximization. The results verify the compatibility of our model with real marketing applications.

The thesis is concerned with problems of algorithm development and programming on primary schools. The main target of the whole thesis is the project of new programming conception, which should bring better results on the field of programming and more effective way of teaching. In theoretic part there are introduced the most important terms from the field of algorithm development and programming, analysis of Czech and foreign education systems, mapping of possibilities of support of teaching from technological and didactical viewpoint. The new programming conception is suggested from theoretical bases. That conception is verified by approximately half-year action research at teaching of programming on 2nd level of primary school. In conclusion of the thesis there are introduced experiences, plusses and minuses of new conception of programming teaching.

In wireless communication, MIMO (multiple input multiple output) is one of the promising technologies which improves the range and performance of transmission without increasing the bandwidth, while providing high rates. High speed hardware MIMO decoders are one of the keys to apply this technology in applications. In order to support the high data rates, the underlying hardware must have significant processing capabilities. FPGA improves the speed of signal processing using parallelism and reconfigurability advantages. The objective of this thesis is to develop an efficient hardware architectural model for the universal lattice decoder and prototype it on FPGA. The original algorithm is modified to ensure the high data rate via taking the advantage of FPGA features. The simulation results of software, hardware are verified and the BER performance of both the algorithms is estimated. The system prototype of the decoder with 4-transmit and 4-receive antennas using a 4-PAM (Pulse amplitude modulation) supports 6.32 Mbit/s data rate for parallelpipeline implementation on FPGA platform, which is about two orders of magnitude faster than its DSP implementation.