[pt] O trabalho consiste de um algoritmo, programado na linguagem LISP/360, que sintetiza uma máquina seqüencial por registros de deslocamento utilizando processos heurísticos. É feita a designação dos estados da máquina e os registros são de mesmo comprimento. Uma parte deste algoritmo consiste de um processo de adição de estados transitórios, tornando qualquer máquina realizável por registros de comprimento - 2. / [en] This paper is concerned with the equal-length shift- register realization of sequential machines. The state assignement is restricted to one code per state. An algorithm programed in LISP/360 is used, which synthesizes a given sequantial machine by shift registers. A part of this algorithm does an addition of transitory states, making possible the synthesis of every sequential machine by shift-registers of length 2.

Artificial Neural networks have found many applications in various fields such as function approximation, time-series prediction, and adaptive control. The performance of a neural network depends on many factors, including the network structure, the selection of activation functions, the learning rate of the training algorithm, and initial synaptic weight values, etc. Genetic algorithms are inspired by Charles Darwin’s theory of natural selection (“survival of the fittest”). They are heuristic search techniques that are based on aspects of natural evolution, such as inheritance, mutation, selection, and crossover. This research utilizes a genetic algorithm to optimize multi-layer feedforward neural network performance and structure. The goal is to minimize both the function of output errors and the number of connections of network. The algorithm is modeled in C++ and tested on several different data sets. Computer simulation results show that the proposed algorithm can successfully determine the appropriate network size for optimal performance. This research also includes studies of the effects of population size, crossover type, probability of bit mutation, and the error scaling factor.

In the design of material handling systems with complex and unpredictable dynamics, conventional search and optimization approaches that are based only on performance measures offer little guarantee of robustness. Using evidence from research into complex systems, the use of behavior-based optimization is proposed, which takes advantage of observed relationships between complexity and optimality with respect to both performance and robustness. Based on theoretical complexity measures, particularly algorithmic complexity, several simple complexity measures are created. The relationships between these measures and both performance and robustness are examined, using a model of a directly connected material handling system as a backdrop. The fundamental causes of the relationships and their applicability in the proposed behavior-based optimization approach are discussed. / Ph. D.

<p>To identify design errors that escape pre-silicon verification, post-silicon validation is becoming an important step in the implementation fl.ow of digital integrated circuits. While many debug problems are tackled on testers, there are hard-to-find design errors that are activated only in-system. A key challenge during in-system debugging is to acquire data from internal circuit's nodes in real-time. In this thesis, we propose several techniques to address this problem, ranging from resource-efficient and programmable trigger units to automated selection of trace signals to a distributed architecture for embedded logic analysis.</p><p>Deciding when to acquire data on-chip is done using trigger units. Because there is an inherent tradeoff between the size of the trigger units and the types of events that can be programmed into them, we first explore a resource-efficient and programmable trigger unit implementation. We show how the on-chip buffers used for data acquisition can be leveraged to store information regarding the logic functions that are programmed at runtime as the trigger events. This reduces the requirement in terms of logic resources for the trigger unit, while enlarging the set of programmable trigger events supported by these resources. We also propose a new algorithm to automatically map trigger events onto the proposed trigger unit.</p><p>Next we shift the focus from the trigger units to the sample units available onchip. Once the real-time debug experiment has been completed, the amount of data available to the user is limited by the capacity of the on-chip trace buffers. For logic bugs, where the circuit implementation matches the physical prototype, we show how the structural information from the circuit netlist can be leveraged to expand the amount of data made available off-line to the user. To ensure that data expansion can scale as the amount of debug data that is acquired increases, we propose a fast algorithm that leverages the bitwise parallelism of logic operations available in the instruction set of microprocessors. In a follow-up chapter, we also discuss how trace signals can be automatically selected in order to improve the amount of data that can be restored off-line. To achieve this objective, we propose two new metrics and two new algorithms for automatically identifying the circuit nodes which, if traced, will aid data expansion for the neighboring nodes in the circuit.</p><p>The last contribution of this thesis is concerned with managing multiple trace buffers in complex designs with many logic blocks. We propose a new distributed embedded logic analysis architecture that can dynamically allocate the trace buffers at runtime based on the needs for debug data acquisition coming from multiple logic blocks. We also leverage the real-time offload capability through high-speed trace ports in order to extend the duration of a debug experiment. It is shown how with little investment in on-chip debug logic resources, the length of debug experiments can be expanded for multi-core designs without increasing the number of on-chip trace buffers.</p> / Thesis / Doctor of Philosophy (PhD)

<p> This thesis examines continued fraction expansions of the square root of nonsquare positive integers of periods one to six, and shows their relationships with Newton's method of approximation. It also contains known results concerning continued fractions.</p> / Thesis / Master of Science (MSc)

<p> The McMaster Incident Detection Algorithm <MacAlg> automatically detects incidents en the Burlington Skyway for the Burlington Freeway Traffic Managment System <FTXS>. This paper describes the calibration, testing and evaluation of functions of northbound stations 1 through 6. The testing and evaluation of the two weekly data sets is illustrated and discussed. Some of the resulting functions are recommended to the Burlingtion FTNS to evaluate how well the MacAlg detects incidents. This research compliments the work: of Persaud, Hall and Hall (1989), who are developing and testing the logic of the MacAlg. The results of this paper contribute information to the further development and testing of the MacAlg's logic. </p> / Thesis / Bachelor of Arts (BA)

This project is an exploration of methods for generating virtual urban environments, framed in an interactive first-person perspective allowing the user to navigate the architectural design space by walking through a city as it is being generated. The project is developed on a foundation of three primary concepts: 1) A spatial interpretation of parameter sets which are positioned in virtual space, 2) Distance-based interpolation of these parameter sets as a method to govern how the urban environments are generated at different points in space,3) The transformation and merging of basic square grids embedded in positioned parameter sets resulting in a composite grid which functions as the spatial framework of the urban environment. The interaction of these concepts forms a framework which allows for the directing of space using 'parametric styles'. This term is in analogy to 'style' in an art-historical sense, which poses questions centered on the formalization and meaning of aesthetics in the context of urban culture, as well as offering an experiment lab for simulating power dynamics between actors in the theory and practice of urban planning and development.

<p>In this dissertation, we propose four novel digital image processing algorithms. First, we discuss a novel digital halftoning algorithm that efficiently removes halftone artifacts commonly associated with error diffusion while adding only an insignificant computational cost. Second, we propose a novel gamut mapping algorithm that utilizes the entire printer gamut resulting in more saturated print results. Third, we propose two digital halftoning algorithms using deep neural networks that generate halftones with quality comparable to those generated with the direct binary search (DBS) algorithm. Lastly, we propose a descreening algorithm based on generative adversarial networks (GAN) framework that generates images with realistic texture.</p>

This dissertation examines the Split Delivery Vehicle Routing Problem (SDVRP), a relaxed version of classical capacitated vehicle routing problem (CVRP) in which the demand of any client can be split among the vehicles that visit it. We study both scenarios of the SDVRP in this dissertation. For the SDVRP with a fixed number of the vehicles, we provide a Two-Stage algorithm. This approach is a cutting-plane based exact method called Two-Stage algorithm in which the SDVRP is decomposed into two stages of clustering and routing. At the first stage, an assignment problem is solved to obtain some clusters that cover all demand points and get the lower bound for the whole problem; at the second stage, the minimal travel distance of each cluster is calculated as a traditional Traveling Salesman Problem (TSP), and the upper bound is obtained. Adding the information obtained from the second stage as new cuts into the first stage, we solve the first one again. This procedure stops when there are no new cuts to be created from the second stage. Several valid inequalities have been developed for the first stage to increase the computational speed. A valid inequality is developed to completely solve the problem caused by the index of vehicles. Another strong valid inequality is created to provide a valid distance lower bound for each set of demand points. This algorithm can significantly outperform other exact approaches for the SDVRP in the literature. If the number of the vehicles in the SDVRP is a variable, we present a column generation based branch and price algorithm. First, a restricted master problem (RMP) is presented, which is composed of a finite set of feasible routes. Solving the linear relaxation of the RMP, values of dual variables are thus obtained and passed to the sub-problem, the pricing problem, to generate a new column to enter the base of the RMP and solve the new RMP again. This procedure repeats until the objective function value of the pricing problem is greater than or equal to zero (for minimum problem). In order to get the integer feasible (optimal) solution, a branch and bound algorithm is then performed. Since after branching, it is not guaranteed that the possible favorable column will appear in the master problem. Therefore, the column generation is performed again in each node after branching. The computational results indicate this approach is promising in solving the SDVRP in which the number of the vehicles is not fixed.

A Network Interface Card (NIC) is used for receiving the packets, processing the packets, passing the packets to the host processor, and sending the packets to other computers in a network. NIC uses the buffer management algorithm to distribute the buffer space among different applications. An application may use User Datagram Protocol (UDP) or Transmission Control Protocol (TCP), depending upon the type of application. Buffer Management Algorithm for UDP-based applications may be completely different from the one for TCP applications, since in UDP- based applications receiver do not send acknowledgement back to the sender. This thesis proposes two buffer management algorithms: 1) Fairly Shared Dynamic Algorithm (FSDA) for UDP-based applications; 2) Evenly Based Dynamic Algorithm (EBDA) for both UDP and TCP-based applications. FSDA utilizes full buffer memory and reduces the packet losses significantly. EBDA reduces packet losses by taking the packet size factor in summation rather than multiplication. This also helps in maintaining fairness among different applications. For the average network traffic load, the FSDA algorithm improves the packet loss ratio by 18.5 % over the dynamic algorithm and by 13.5% over the DADT, while EBDA improves by 16.7 % over the dynamic algorithm and by 11.8% over the DADT. For the heavy network traffic load, the FSDA algorithm improves the packet loss ratio by 16.8 % over the dynamic algorithm and by 12.5% over the DADT while EBDA improves the packet loss ratio by 16.8 % over the dynamic algorithm and by 12.6% over the DADT. For the actual traffic load, the improvement over DA and DADT is 13.6% and 7.5% for FSDA and 7.6% and 1.9% for EBDA.