In this thesis different aspects of general low power design and LNA-design have been studied. A new architecture for an ultra low power LNA is proposed and simple simulation results are presented. Simulations show that there should be possible to design a 2.4 GHz LNA that works sufficiently at 200 µA. The proposed architecture achieved a voltage gain over 20 dB from 2.32 to 2.5 GHz, a noise figure of 4.65 dB, IIP3 of -15.45 dBm and a input match of -9.5 dB. There is still a lot of work do and many simulations to perform before one can inconclusively conclude that the proposed architecture is a feasible solution, although the results generated in this thesis seem promising.

In this thesis different aspects of general low power design and LNA-design have been studied. A new architecture for an ultra low power LNA is proposed and simple simulation results are presented. Simulations show that there should be possible to design a 2.4 GHz LNA that works sufficiently at 200 µA. The proposed architecture achieved a voltage gain over 20 dB from 2.32 to 2.5 GHz, a noise figure of 4.65 dB, IIP3 of -15.45 dBm and a input match of -9.5 dB. There is still a lot of work do and many simulations to perform before one can inconclusively conclude that the proposed architecture is a feasible solution, although the results generated in this thesis seem promising.

This work documents the important design considerations and high--level development of an efficient Continuous-Time DS A/D converter for given system requirements. Projecting characteristics is especially essential in the design of the option-versatile DS converter and involves both advanced control and signaling theory, in addition to circuit and system design. Thus, extensive simulations were carried out through synthesis and behavioral modelling.Synthesis was performed using R. Schreiers DS toolbox while modelling was done using the framework of Cadence with Virtuoso and Spectre. Behavioral modelling was based on the mixed-signaling language VerilogA. A list of candidates, meeting the performance requirements set, were formed from synthesis and two modulator architectures stood out; a multi-bit third order and a single-bit fifth order, both with an oversampling ratio of 32. Both feedback and feedforward loop filter structures were analyzed.A useful and powerful analysis was carried out to characterize and quantify the impact of location on nonidealities in DS modulators. The model was prepared for verification, helping to analyze, characterize and specify crucial parts of each structure. Decisive nonidealities, such as excess loop delay, finite DC gain, limited GBW, circuit noise and their influence on the overall modulator were included and examined. From this, a specification for the integrators as well as a preliminary noise and power budget was established.The final result ends in a realistic environment capable of analyzing different types of CTDS structures and making an informed decision on the most optimal and suitable configuration. Results from synthesis and behavioral modelling showed a great correspondance between the results obtained in each part. After an iterative process of evaluating performance among other metrics with nonideal effects, the best architecture was found to be the third order multi-bit feedback modulator, which achieved all of the requirements while consuming 3724uW

The objective of this thesis was to design a power-efficient general purpose SAR ADC. The ADC's requirements were set by Energy Micro, favoring a very high performance-to-power ratio. The requirements are based on the present Energy Micro ADC, but with a 67% reduction in current consumption, a more modern CMOS technology of 90nm and a supply voltage of 1.2V.A full SAR ADC model was made using SPICE and VHDL code for the analog and digital sub-systems, respectively. The comparator was thoroughly designed and optimized, to achieve enough performance with as little power as possible. Then the total capacitor value of the sub-DAC was minimized, using extra reference voltages, minimizing the dynamic power consumption of the reference voltage generator. An asynchronous clock was also implemented, substantially increasing the available settling times of the comparator.The result was a very power-efficient SAR ADC, which fulfills the power-consumption requirement with 114$mu$J per conversion. Compared to other, similar SAR ADC's which has been researched, the ADC designed in this thesis is found to be very power-efficient. There might be some linearity problems in the ADC, partly from the transmission gates used as switches, but the overall design seems promising.

The low noise amplifier is a critical part of most high performance ultrasoundreceivers, and is important for achieving high sensitivity and a wide dynamic range.By having a large gain in the low noise amplifier, the total noise of the receiversystem will be dominated by that of the amplifier. For most low noise amplifier,there is a fundamental trade–off between accuracy and power consumption, whichmakes it difficult to design micro power front–end amplifiers with excellent noiseperformance. In some cases, however, lower accuracy can be tolerated if the sourceitself is noisy. This is the case for small, high impedance sources, where the noiselevel is in the region of 18 nV/sqrt{Hz}.This thesis presents the design and simulations of a low noise amplifier instandard 180 nm CMOS suitable for use with high impedance sources. In fact,high impedance sources pose challenges on the biasing of voltage amplifiers,where maintaining high input impedance is necessary. In addition, for differentialamplifiers, implementing common–mode feedback will typically result in a significantincrease in power consumption and area overhead. To alleviate this problem, aswitched common–mode feedback scheme is implemented, that also provide highinput impedance biasing of the input transistors.In order to cope with the large dynamic range requirement inherent in manyultrasound modalities, variable gain is often used to compress the dynamic rangefor the analog front–end. Methods for adding variable gain without resulting in alarge increase in area and power consumption is therefore of huge interest in manyultrasound applications. Several methods of adding variable gain is investigated inthis thesis, and a capacitive attenuator is proposed, which causes minimum increasein noise factor, while increasing the gain range by at least 20 dB.Large scale integration of several thousands analog front–ends in a singleultrasound probe handle requires low power consumption and minimum areaoverhead for all parts of the analog front–end, including the low noise amplifier.By using a figure–of–merit based optimization technique, the designed amplifiertopology achieves an low power consumption of 17.3 μA, while maintaining a noisefactor of less than 3 dB at resonance. In addition to performing a single–ended todifferential conversion, this amplifier realizes a maximum voltage gain of 23.4 dB,with a 3 dB bandwidth of 21.5 MHz.

This thesis presents an ultra-low-power 8-bit asynchronous current-modesuccessive approximation (SAR) ADC for single channel neuron spike recording.The novel design exploits current mode operating in weak inversion forhigh power efficiency and is designed to operate at a 1.8V supply. The ADC isrunning at a 16kHz sampling frequency using under 1uW of power, thoughis adjustable using the featured calibration registers. A finished layout ispresented, occupying less than 0.078mm2. Linear operation through mismatchand process variations is obtained using a current calibration circuitconnected to both the current mode DAC and all the biases. This ensuresINL < 0.5 and DNL < 1, yielding no missing codes and a 3sigma productionyield. Calibration is needed because of the relatively large mismatch causedby sub-threshold operation of the current mirrors. The design also offers anewly developed current comparator with high resolution and fast settlingrelative to the current level and is completable with other state-of-the-art solutions,though still feature some voltage scaling issues left for future work.

A 9-bit 50M S/s dual-residue pipelined ADC is modeled and analyzed. Thefirst stage is a modified pipelined ADC stage, while the other stages uses aninterpolator to resolve the signals, the focus is on designing these stages. Thedual-residue architecture is insensitive to the gain of the residue amplifiers, andonly a matching between two amplifiers is necessary. Limiting parameters of theADC is the offset in the residue amplifiers, as well as gain mismatch betweenthe amplifiers. The maximum allowed offset voltage of the residue amplifier isVlsb/2 , and maximum allowable mismatch between the two residue amplifiers is 1/256 for a 9-bit ADC. Multiple amplifier topologies were discussed and the bestcandidate for residue amplification is found to be a zero-crossing based amplifier.With this type of amplifier the last 8 stages of the ADC has an estimated powerconsumption of 2.1mW.

This thesis presents a fully differential 9-bit current-mode successive approximation (SAR) ADC. The circuit is designed in 0.18 um technology with 1.8 V supply voltage and has a current draw on 472 uA. The ADC has a sampling frequency on 50 MHz and has a maximum ENOB on 8.42 bit. Because of non-linearity will ENOB be input frequency dependent and degrade to 6.87 bit.The design is based on conventional current-mode SAR ADC operation, but with a new comparator design and time interleaving. Time interleaving is used to increase the sampling frequency 10 times.The circuit needs a high degree of matching to work properly. Sub-threshold operation in several current sources gives a high degree of uncertainty in the current value. Thus several calibration circuits are presented, but are not implemented.