This thesis focuses on the design and implementation of low power Σ∆ ADCs in 130 nanometer CMOS technology. The design issues in the implementation of a third order ADC with a multi-bit and single bit quantizer are discussed. The advancement in CMOS technology has led to designing as much of electronics systems as possible with the digital circuits and digital signal processing replacing analog processing in most cases. Hence there is a need for digitizing analog signals with analog to digital converter (ADC). In communication systems this needs to be done immediately after the antenna in a receiver system. As this is difficult to implement due to high speed and high power consumption, RF signal is converted to a lower intermediate frequency (IF) and digitized. This work stresses low power implementation of high bandwidth Σ∆ ADCs for digitizing the IF. Design techniques involved in the implementation of a third order continuous time Σ∆ ADC with a 4 bit quantizer as well as a single bit quantizer for wide bandwidth are discussed. Moreover, a third order continuous time audio ADC implementation was also done. The behavioural modelling of the Σ∆ ADC along with clock jitter non-linearity model was developed and the issues in circuit design techniques are addressed. The continuous time ADCs’ major problem, namely, excess loop delay is discussed in detail and an efficient compensation technique for the same is implemented which allows a large reduction of power consumed by the ADC. Choice of loop filter architecture, quantizer and transistor level implementation are given that result in better immunity to offsets and process variations. Both the ADCs have been implemented using UMC 130 nm Mixed-mode RF-CMOS process and the simulation results for the multi-bit ADC gives a peak SNR of 56dB with a dynamic range of 65dB with power consumption of 2mW. The audio ADC achieves a peak SNR of 94.2dB with a dynamic range of 91dB.