Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.

In this thesis we discuss design and implementation of low-complexity digital filters. Digital filters are key components in most digital signal processing (DSP) systems and are, for example, used for interpolation and decimation. A typical application for the filters considered in this work is mobile communication systems, where high throughput and low power consumption are required. In the first part of the thesis we discuss implementation of high throughput lattice wave digital filters (LWDFs). Here arithmetic transformation of first- and second-order Richards’ allpass sections are proposed. The transformations reduces the iteration period bound of the filter realization, which can be used to increase the throughput or reduce the power consumption through power supply voltage scaling. Implementation of LWDFs using redundant, carry-save arithmetic is considered and the proposed arithmetic transformations are evaluated with respect to throughput and area requirements. In the second part of the thesis we discuss three case studies of implementations of digital filters for typical applications with requirements on high throughput and low power consumption. The first involves the design and implementation of a digital down converter (DDC) for a multiple antenna element radar receiver. The DDC is used to convert a real IF input signal into a complex baseband signal composed of an inphase and a quadrature component. The DDC includes bandpass sampling, digital I/Q demodulation, decimation, and filtering and three different DDC realizations are proposed and evaluated. The second case study is a combined interpolator and decimator filter for use in an OFDM system. The analog-to-digital converters (ADCs) and the digital-to-analog converters (DACs) work at a sample rate twice as high as the Nyquist rate. Hence, interpolation and decimation by a factor of two is required. Also, some channel shaping is performed which complicates the filter design as well as the implementation. Frequency masking techniques and novel filter structures was used for the implementation. The combined interpolator and decimator was successfully implemented using an LWDF in a 0.35 mm CMOS process using carry-save arithmetic. The third case study is the implementation of a high-speed decimation filter for a SD ADC. The decimator has an input data rate of 16 Gsample/s and the decimation factor is 128. The decimation is performed using two cascaded digital filters, a comb filter followed by a linear-phase FIR filter. A novel hardware structure for single-bit input digital filters is proposed. The proposed structure was found to be competitive and was used for the implementation. The decimator filter was successfully implemented in a 0.18 mm CMOS process using standard cells. In the third part of the thesis we discuss efficient realization of sum-of-products and multiple-constant multiplications that are used in, for example, FIR filters. We propose several new difference methods that result in realizations with a low number of adders. The proposed design methods have low complexity, i.e., they can be included in the search for quantized filter coefficients.

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