Analog-to-digital converter (ADC) is the main workhorse in a digital waveform recorder. Strictly speaking, an ADC is supposed to perform uniformly, irrespective of the characteristics of the signal to be acquired. However, because of certain hardware related inconsistencies, its performance declines, particularly, when acquiring non-repetitive, fast-rising, high frequency signals. The error and distortion contributed due to its declining performance, for the entire range of signals, can be comprehensively characterized by the static and dynamic nonlinearities. Actual testing of ADCs is the only way of estimating these indices. These characteristics reveal information at the microscopic level, such as bit-level aberrations, code transitions, response and settling trends, etc. These tests attain greater significance, when the digitizer is part of a reference measuring or a calibration system, because, the levels of accuracies to be achieved in such a setup may become comparable to the error introduced by the ADC. Hence, testing ADCs is a priority. International and national standards exist for testing digital waveform recorders and ADCs. For several years, the matter related to reducing static test time of high-resolution ADCs was highlighted through many publications. A critical examination of the literature indicates the major schools-of-thought pursued so far, are, (i) refinements to ramp/triangular signal based static testing, (ii) proposals for use of alternative methods and/or test signals for static test, (iii) innovative ways of achieving a relaxation in signal source requirements and, (iv) efforts to combine static and dynamic test into a single test with an appropriate test signal. As a consequence of the literature review, objectives of the thesis were formulated. They attempt to resolve- (i) Conceive a suitable test signal for simultaneous estimation of static and dynamic nonlinearity through a single test (ii) Explore possibility of employing a low-linearity ramp signal to estimate static nonlinearity (iii) Estimating static nonlinearity by exploiting linearity property of a sine signal • In the first part of the thesis, a method is proposed for the concurrent estimation of static and dynamic nonlinearity characteristics of an ADC, with the application of a single test signal. The novelty arises from the fact that the test signal proposed is new, and so is the concept of extracting the static and dynamic nonlinearity from the ADC output. This was achieved by conceiving a test signal, comprising of a high frequency sinusoid (which addresses the dynamic requirement), modulated by a low frequency ramp (which addresses the static requirement). • Static characteristics of an ADC can be determined directly from the histogram-based quasi-static approach by measuring the ADC output, when excited by an ideal ramp/triangular signal of sufficiently low frequency. This approach requires only a fraction of time compared to the conventional DC test, is straightforward, easy to implement, and, in principle is an accepted method as per the revised IEEE-1057. However, the only drawback is that ramp signal sources are not ideal. Thus, nonlinearity present in the ramp signal gets superimposed on the measured ADC characteristics, which renders them, as such, unusable. The second part of the work describes a proposal to get rid of the ramp signal nonlinearity, before it is applied to the ADC. A simple method is presented which employs a low-linearity ramp signal, but yet causes only a fraction of influence on the measured ADC static characteristics. • The third part of the thesis describes a novel method to estimate the actual static characteristics of an ADC using a low frequency sine signal, say, less than 10 Hz, by employing the histogram-based approach. It is based on the well known fact that variation of sine signal is ‘reasonably linear,’ when the angle is small. In the proposed method, the ADC under test has to be ‘fed’ with this ‘linear’ portion of the sine wave. Due to harmonics and offset in input excitation, this ‘linear’ part of the sine signal is marginally different, compared to an ideal ramp signal of equal amplitude. However, since it is a sinusoid, this difference can be accurately determined and later compensated from the measured ADC output. Thus, the corrected ADC output will correspond to the true ADC static nonlinearity. The proposed approach successfully addresses all the three concerns while estimating static linearity, i.e. it is time-efficient, excites all the ADC code-bins reasonably uniformly and tackles the source linearity issue quite nicely. These proposals are novel, simple, easy to implement, time-efficient and importantly static nonlinearity characteristics determined from them are in good agreement with that estimated by the original DC-based technique. Implementation of each method is discussed along with experimental results, for two 8-bit digital oscilloscopes and a 10-bit real time digitizer. Further details are presented in the thesis.

Sensor interfaces are needed to communicate the measured real-world analog values to the base¬band digital processor. They are dominated by the presence of high accuracy, high resolution analog to digital converters (ADC) in the backend. On most occasions, sensing is limited to small range measurements and low-modulation sensors where the complete dynamic range of ADC is not utilized. Designing a subsystem that integrates the sensor and the interface circuit and that works with a low resolution ADC requiring a small die-area is a challenge. In this work, we present a CMOS based area efficient, integrated sensor interface for applications like capacitance, temperature and dielectric-constant measurement. In addition, potential applica-tions for this work are in Cognitive Radios, Software Defined Radios, Capacitance Sensors, and location monitoring. The key contributions in the thesis are: 1 High Sensitivity Frequency-domain CMOS Capacitance Interface: A frequency domain capacitance interface system is proposed for a femto-farad capacitance measurement. In this technique, a ring oscillator circuit is used to generate a change in time period, due to a change in the sensor capacitance. The time-period difference of two such oscillators is compared and is read-out using a phase frequency detector and a charge pump. The output voltage of the system, is proportional to the change in the input sensor capacitance. It exhibits a maximum sensitivity of 8.1 mV/fF across a 300 fF capacitance range. 2 Sensitivity Enhancement for capacitance sensor: The sensitivity of an oscillator-based differential capacitance sensor has been improved by proposing a novel frequency domain capacitance-to-voltage (FDC) measurement technique. The capacitance sensor interface system is fabricated in a 130-nm CMOS technology with an active area of 0.17mm2 . It exhibits a maximum sensitivity of 244.8 mV/fF and a measurement resolution of 13 aF in a 10-100 fF measurement range, with a 10 pF nominal sensor capacitance and an 8-bit ADC. 3 Frequency to Digital Converter for Time/Distance measurement: A new architecture for a Vernier-based frequency-to-digital converter (VFDC) for location monitoring is pre¬sented, in which, a time interval measurement is performed with a frequency domain approach. Location monitoring is a common problem for many mobile robotic applica¬tions covering various domains, such as industrial automation, manipulation in difficult areas, rescue operations, environment exploration and monitoring, smart environments and buildings, robotic home appliances, space exploration and probing. The proposed architecture employs a new injection-locked ring oscillator (ILR) as the clock source. The proposed ILR oscillator does not need complex calibration procedures, usually required by Phase Locked Loop (PLL) based oscillators in Vernier-based time-to-digital convert¬ers. It consumes 14.4 µW and 1.15 mW from 0.4 V and 1.2 V supplies, respectively. The proposed VFDC thus achieves a large detectable range, fine time resolution, small die size and low power consumption simultaneously. The measured time-difference error is less than 50 ps at 1.2 V, enabling a resolution of 3 mm/kHz frequency shift. 4 A bio-sensor array for dielectric constant measurement: A CMOS on-chip sensor is presented to measure the dielectric constant of organic chemicals. The dielectric constant of these chemicals is measured using the oscillation frequency shift of a current controlled os¬cillator (CCO) upon the change of the sensor capacitance when exposed to the liquid. The CCO is embedded in an open-loop frequency synthesizer to convert the frequency change into voltage, which can be digitized using an off-chip analog-to-digital converter. The dielectric constant is then estimated using a detection procedure including the calibration of the sensor. 5 Integrated Temperature Sensor for thermal management: An integrated analog temper¬ature sensor which operates with simple, low-cost one-point calibration is proposed. A frequency domain technique to measure the on-chip silicon surface temperature, was used to measure the effects of temperature on the stability of a frequency synthesizer. The temperature to voltage conversion is achieved in two steps i.e. temperature to frequency, followed by frequency to voltage conversion. The output voltage can be used to com¬pensate the temperature dependent errors in the high frequency circuits, thereby reduc¬ing the performance degradation due to thermal gradient. Furthermore, a temperature measurement-based on-chip self test technique to measure the 3 dB bandwidth and the central frequency of common radio frequency circuits, was developed. This technique shows promise in performing online monitoring and temperature compensation of RF circuits.