Abstract Anisotropic wet etching is one of the key technologies for the microstructure fabrication in Micro Electro Mechanical Systems (MEMS). Agitation technique is one of the key parameters to affect significantly the quality of silicon anisotropic wet etching, which includes the etch rate and surface roughness. In general, magnetic stirring is used during silicon anisotropic wet etching operation. The ultrasonic agitation and add surfactant have been to replaced and to proceed a series of experiment for KOH solution and TMAH solution in this study. The results show that the ultrasonic agitation can reduce the surface roughness and achieve the high-quality etching surface, its roughness even is only about Ra 47.5Å. Besides, the etch rate is also increased slightly. But it is easily to cause the damage of the microstructure. The addition of anionic surfactant to the KOH solution without any agitation condition can achieve the same at the etching performance of the ultrasonic agitation. The addition of anionic surfactant and nonionic surfactant to the TMAH solution without any agitation condition can achieve the same at the etching performance of the ultrasonic agitation. TMAH solution adds nonionic surfactant not only improves the surface roughness, but also retards the phenomenon of the undercut. Keyword¡Ganisotropic wet etching, magnetic stirring, ultrasonic, surfactant

This thesis presents the development of electrochemical etch-stop techniques (ECES) to achieve high precision 3-dimensional integrated MEMS sensors with wet anisotropic etching by applying proper voltages to various regions in silicon. The anisotropic etchant is selected as tetra methyl ammonium hydroxide, TMAH, considering its high silicon etch rate, selectivity towards SiO2, and CMOS compatibility, especially during front-side etching of the chip/wafer. A number of parameters affecting the etching are investigated, including the effect of temperature, illumination, and concentration of the etchant over the etch rate of silicon, surface roughness, and biasing voltages. The biasing voltages for passivating the n-well and enhancing the etching reactions on p-substrate are determined as -0.5V and -1.6V, respectively, after a series of current-voltage characteristic experiments. The surface roughness due to TMAH etching is prevented with the addition of ammonium peroxodisulfate, AP. A proper etching process is achieved using a 10wt.% TMAH at 85&deg / C with 10gr/lt. AP. Different silicon etch samples are produced in METU-MET facilities to understand and optimize ECES parameters that can be used for CMOS microbolometers. The etch samples are fabricated using various processes, including thermal oxidation, boron and phosphorus diffusions, aluminum and silicon nitride layer deposition processes. Etching with the prepared samples shows the dependency of the depletion layer between p-substrate and n&amp / #8209 / well, explaining the reason of the previous failures during post-CMOS etching of CMOS microbolometers from the front side. Succesfully etched CMOS microbolometers are achieved with back side etching in 6M KOH at 90 &deg / C, where &amp / #8209 / 3.5V and 1.5V are applied to the p-substrate and n-well. In summary, this study provides an extensive understanding of the ECES process for successful implementations of integrated MEMS sensors.

The continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes. / text

The task of master’s thesis was to perform optimalization process for preparing metal etching mask by electron beam litography and subsequent selective wet ething of silicon with crystalographic orientation (100). Further characterization of etched surface and fabricated structures was performed. In particular, attention was given to the morphology demonstrated by scanning electron microscopy and study changes of the optical properties of gold plasmonic antennas due to their undercut.