Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Yalamanchili, Sudhakar; Committee Member: Riley, George; Committee Member: Schimmel, David. Part of the SMARTech Electronic Thesis and Dissertation Collection.

The thesis focuses on the construction and symbolic encoding of Prague from 1945 to the late 1950s, with emphasis on the Stalinist era. Based on an analysis of historical texts and architectural projects, the thesis studies the motivations and tactics, which the post-war political and professional elites sought to manifest their own values and ideological principles in the area of the capital city. Through the analysis of historical concepts of "old" and "new" Prague examines the thesis the changing relationship between tradition and modernity in the image of the city. The sociocultural phenomenon of Stalinism is thematized as a specific part of the long process of modernization, which passes through Prague during the first half of the 20th century. The thesis deals also with the attributes that should characterize the "new" socialist Prague and with the ways of using the Soviet patterns and local historical traditions. Keywords: Prague, city, image of the city, architecture, urbanism, memory, heritage, socialist realism, stalinism, 1950s

In computing the available computing power has continuously fallen short of the demanded computing performance. As a consequence, performance improvement has been the main focus of processor design. However, due to the phenomenon called 'Power Wall' it has become infeasible to build faster processors by just increasing the processor's clock speed. One of the resulting trends in hardware design is to integrate several simple and power-efficient cores on the same chip. This design shift poses challenges of its own. In the past, with increasing clock frequency the programs became automatically faster as well without modifications. This is no longer true with many-core architectures. To achieve maximum performance the programs have to run concurrently on more than one core, which forces the general computing paradigm to become increasingly parallel to leverage maximum processing power. In this thesis, we will focus on the Reactive Stream Program (RSP). In stream processing, the system consists of computing nodes, which are connected via communication streams. These streams simplify the concurrency management on modern many-core architectures due to their implicit synchronisation. RSP is a stream processing system that implements the reactive system. The RSPs work in tandem with their environment and the load imposed by the environment may vary over time. This provides a unique opportunity to increase performance per watt. In this thesis the research contribution focuses on the design of the execution layer to run RSPs on tiled many-core architectures, using the Intel's Single-chip Cloud Computer (SCC) processor as a concrete experimentation platform. Further, we have developed a Dynamic Voltage and Frequency Scaling (DVFS) technique for RSP deployed on many-core architectures. In contrast to many other approaches, our DVFS technique does not require the capability of controlling the power settings of individual computing elements, thus making it applicable for modern many-core architectures, with which power can be changed only for power islands. The experimental results confirm that the proposed DVFS technique can effectively improve the energy efficiency, i.e. increase the performance per watt, for RSPs.