<p>To counter radio signal reconnaissance, an efficient way of covert communication is to use subsecond duration burst transmissions in the congested HF band. Against this background, the present thesis treats fast direction finding (DF) using antenna arrays with known response only in a few calibration directions. In such scenarios the known method of array mapping (interpolation) may be used to transform the output data vectors from the existing array onto the corresponding output vectors of another (virtual) array that is mathematically defined and optimally chosen. But in signal reconnaissance the emitters are initially unknown and the mapping matrix must be designed as a compromise over a wide sector of DOAs. This compromise may result in large DOA estimate errors, both deterministic and random. Analyzing, analytically describing, and minimizing these DOA errors, is the main theme of the present thesis. The first part of the thesis analyzes the deterministic mapping errors, the DOA estimate bias, that is caused by dissimilarity between the two array geometries. It is shown that in a typical signal reconnaissance application DOA estimate bias can dominate over DOA estimate variance. Using a Taylor series expansion of the DOA estimator cost function an analytical expression for the bias is derived and a first order zero bias condition is identified. This condition is general, estimator independent, and can be applied to any type of data pre-processing. A design algorithm for the mapping matrix is thereafter presented that notably reduces mapped DOA estimate bias. A special version is also given with the additional property of reducing the higher order Taylor terms and thus the residual bias. Simulations demonstrate a bias reduction factor exceeding 100 in some scenarios. A version based on signal subspace mapping rather than array manifold mapping is also given. This version is of large practical interest since the mapping matrix can be designed directly from calibration data. In the second part of the thesis the derived bias minimization theory is extended into Mean Square Error (MSE) minimization, i.e. measurement noise is introduced. Expressions for DOA error variance and DOA MSE under general pre-processing are derived, and a design algorithm for the mapping matrix is formulated by which mapped DOA estimate MSE can be minimized. Simulations demonstrate improved robustness and performance for this algorithm, especially in low SNR scenarios. In the third and final part of the thesis the theoretical results are supported by experimental data. For an 8 element circular array mapped onto a virtual ULA across a 600 sector it is shown that the mapped DOA estimate errors can be suppressed down to the Cramér-Rao level.</p>

To counter radio signal reconnaissance, an efficient way of covert communication is to use subsecond duration burst transmissions in the congested HF band. Against this background, the present thesis treats fast direction finding (DF) using antenna arrays with known response only in a few calibration directions. In such scenarios the known method of array mapping (interpolation) may be used to transform the output data vectors from the existing array onto the corresponding output vectors of another (virtual) array that is mathematically defined and optimally chosen. But in signal reconnaissance the emitters are initially unknown and the mapping matrix must be designed as a compromise over a wide sector of DOAs. This compromise may result in large DOA estimate errors, both deterministic and random. Analyzing, analytically describing, and minimizing these DOA errors, is the main theme of the present thesis. The first part of the thesis analyzes the deterministic mapping errors, the DOA estimate bias, that is caused by dissimilarity between the two array geometries. It is shown that in a typical signal reconnaissance application DOA estimate bias can dominate over DOA estimate variance. Using a Taylor series expansion of the DOA estimator cost function an analytical expression for the bias is derived and a first order zero bias condition is identified. This condition is general, estimator independent, and can be applied to any type of data pre-processing. A design algorithm for the mapping matrix is thereafter presented that notably reduces mapped DOA estimate bias. A special version is also given with the additional property of reducing the higher order Taylor terms and thus the residual bias. Simulations demonstrate a bias reduction factor exceeding 100 in some scenarios. A version based on signal subspace mapping rather than array manifold mapping is also given. This version is of large practical interest since the mapping matrix can be designed directly from calibration data. In the second part of the thesis the derived bias minimization theory is extended into Mean Square Error (MSE) minimization, i.e. measurement noise is introduced. Expressions for DOA error variance and DOA MSE under general pre-processing are derived, and a design algorithm for the mapping matrix is formulated by which mapped DOA estimate MSE can be minimized. Simulations demonstrate improved robustness and performance for this algorithm, especially in low SNR scenarios. In the third and final part of the thesis the theoretical results are supported by experimental data. For an 8 element circular array mapped onto a virtual ULA across a 600 sector it is shown that the mapped DOA estimate errors can be suppressed down to the Cramér-Rao level. / QC 20101022

Der technologische Fortschritt gestattet die Implementierung zunehmend komplexerer Prozessorarchitekturen auf einem Schaltkreis. Ein Trend der letzten Jahre ist die Implementierung von mehr und mehr Verarbeitungseinheiten auf einem Chip. Daraus ergeben sich neue Herausforderungen für die Abbildung von Algorithmen auf solche Architekturen, denn alle Verarbeitungseinheiten sollen effizient bei der Ausführung des Algorithmus genutzt werden. Der Schwerpunkt der eingereichten Dissertation ist die Ausnutzung der Parallelität von Rechenfeldern mit Teilwortparallelität. Solche Architekturen erlauben Parallelverarbeitung auf mehreren Ebenen. Daher wurde eine Abbildungsstrategie, mit besonderem Schwerpunkt auf Teilwortparallelität entwickelt. Diese Abbildungsstrategie basiert auf den Methoden des Rechenfeldentwurfs. Rechenfelder sind regelmäßig angeordnete Prozessorelemente, die nur mit ihren Nachbarelementen kommunizieren. Die Datenein- und -ausgabe wird durch die Prozessorelemente am Rand des Rechenfeldes realisiert. Jedes Prozessorelement kann mehrere Funktionseinheiten besitzen, welche die Rechenoperationen des Algorithmus ausführen. Die Teilwortparallelität bezeichnet die Fähigkeit zur Teilung des Datenpfads der Funktionseinheit in mehrere schmale Datenpfade für die parallele Ausführung von Daten mit geringer Wortbreite. Die entwickelte Abbildungsstrategie unterteilt sich in zwei Schritte, die \"Vorverarbeitung\" und die \"Mehrstufige Modifizierte Copartitionierung\" (kurz: MMC). Die \"Vorverarbeitung\" verändert den Algorithmus in einer solchen Art, dass der veränderte Algorithmus schnell und effizient auf die Zielarchitektur abgebildet werden kann. Hierfür wurde ein Optimierungsproblem entwickelt, welches schrittweise die Parameter für die Transformation des Algorithmus bestimmt. Die \"Mehrstufige Modifizierte Copartitionierung\" wird für die schrittweise Anpassung des Algorithmus an die Zielarchitektur eingesetzt. Darüber hinaus ermöglicht die Abbildungsmethode die Ausnutzung der lokalen Register in den Prozessorelementen und die Anpassung des Algorithmus an die Speicherarchitektur, an die das Rechenfeld angebunden ist. Die erste Stufe der MMC dient der Transformation eines Algorithmus mit Einzeldatenoperationen in einen Algorithmus mit teilwortparallelen Operationen. Mit der zweiten Copartitionierungsstufe wird der Algorithmus an die lokalen Register und an das Rechenfeld angepasst. Weitere Copartitionierungsstufen können zur Anpassung des Algorithmus an die Speicherarchitektur verwendet werden. / The technological progress allows the implementation of complex processor architectures on a chip. One trend of the last years is the implemenation of more and more execution units on one chip. That implies new challenges for the mapping of algorithms on such architectures, because the execution units should be used efficiently during the execution of the algorithm. The focus of the submitted dissertation thesis is the utilization of the parallelism of processor arrays with subword parallelism. Such architectures allow parallel executions on different levels. Therefore an algorithm mapping strategy was developed, where the exploitation of the subword parallelism was in the focus. This algorithm mapping strategy is based on the methods of the processor array design. Processor arrays are regular arranged processor elements, which communicate with their neighbors elements only. The data in- and output will be realized by the processor elements on the border of the array. Each processor element can have several functional units, which execute the computational operations. Subword parallelism means the capability for splitting the data path of the functional units in several smaller chunks for the parallel execution of data with lower word width. The developed mapping strategy is subdivided in two steps, the \"Preprocessing\" and the \"Multi-Level Modified Copartitioning\" (kurz: MMC), whereat the MMC means the method of the step simultaneously. The \"Preprocessing\" alter the algorithm in such a kind, that the altered algorithm can be fast and efficient mapped on the target architecture. Therefore an optimization problem was developed, which determines gradual the parameter for the transformation of the algorithm. The \"Multi-Level Modified Copartitioning\" is used for mapping the algorithm gradual on the target architecture. Furthermore the mapping methodology allows the exploitation of the local registers in the processing elements and the adaptation of the algorithm on the memory architecture, where the processing array is connected on. The first level of the MMC is used for the transformation of an algorithm with operation based on single data to an algorithm with subword parallel operations. With the second level, the algorithm will be adapted to the local registers in the processing elements and to the processor array. Further copartition levels can be used for matching the algorithm to the memory architecture.