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by Vincent Wing-Yun Sit. / Thesis submitted in: June 1997. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 1-4 (3rd gp.)). / Abstract also in Chinese. / TABLE OF CONTENTS / LIST OF FIGURES / LIST OF TABLES / ACKNOWLEDGEMENTS / ABSTRACT / Chapter 1. --- INTRODUCTION --- p.1 / Chapter 1.1 --- ASYNCHRONOUS DESIGN --- p.2 / Chapter 1.1.1 --- POTENTIAL ADVANTAGES --- p.2 / Chapter 1.1.2 --- DESIGN METHODOLOGIES --- p.2 / Chapter 1.1.3 --- SYSTEM CHARACTERISTICS --- p.3 / Chapter 1.2 --- ASYNCHRONOUS MEMORY --- p.5 / Chapter 1.2.1 --- MOTIVATION --- p.5 / Chapter 1.2.2 --- DEFINITION --- p.9 / Chapter 1.3 --- PROPOSED MEMORY DESIGN --- p.10 / Chapter 1.3.1 --- CONTROL INTERFACE --- p.10 / Chapter 1.3.2 --- OVERVIEW --- p.11 / Chapter 1.3.3 --- HANDSHAKE CONTROL PROTOCOL --- p.13 / Chapter 2. --- THEORY --- p.16 / Chapter 2.1 --- VARIABLE BIT LINE LOAD --- p.17 / Chapter 2.1.1 --- DEFINITION --- p.17 / Chapter 2.1.2 --- ADVANTAGE --- p.17 / Chapter 2.2 --- CURRENT SENSING COMPLETION DETECTION --- p.18 / Chapter 2.2.1 --- BLOCK DIAGRAM --- p.19 / Chapter 2.2.2 --- GENERAL LSD CURRENT SENSOR --- p.21 / Chapter 2.2.3 --- CMOS LSD CURRENT SENSOR --- p.23 / Chapter 2.3 --- VOLTAGE SENSING COMPLETION DETECTION --- p.28 / Chapter 2.3.1 --- DATA READING IN MEMORY CIRCUIT --- p.29 / Chapter 2.3.2 --- BLOCK DIAGRAM --- p.30 / Chapter 2.4 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.32 / Chapter 2.4.1 --- ADVANTAGE --- p.32 / Chapter 2.4.2 --- BLOCK DIAGRAM --- p.33 / Chapter 3. --- IMPLEMENTATION --- p.35 / Chapter 3.1 --- 1M-BIT SRAM FRAMEWORK --- p.36 / Chapter 3.1.1 --- INTRODUCTION --- p.36 / Chapter 3.1.2 --- FRAMEWORK --- p.36 / Chapter 3.2 --- CONTROL CIRCUIT --- p.40 / Chapter 3.2.1 --- CONTROL SIGNALS --- p.40 / Chapter 3.2.1.1 --- EXTERNAL CONTROL SIGNALS --- p.40 / Chapter 3.2.1.2 --- INTERNAL CONTROL SIGNALS --- p.41 / Chapter 3.2.2 --- READ / WRITE STATE TRANSITION GRAPHS --- p.42 / Chapter 3.2.3 --- IMPLEMENTATION --- p.43 / Chapter 3.3 --- BIT LINE SEGMENTATION --- p.45 / Chapter 3.3.1 --- FOUR REGIONS SEGMENTATION --- p.46 / Chapter 3.3.2 --- OPERATION --- p.50 / Chapter 3.3.3 --- MEMORY CELL --- p.51 / Chapter 3.4 --- CURRENT SENSING COMPLETION DETECTION --- p.52 / Chapter 3.4.1 --- ONE BIT DATA BUS --- p.53 / Chapter 3.4.2 --- EIGHT BITS DATA BUS --- p.55 / Chapter 3.5 --- VOLTAGE SENSING COMPLETION DETECTION --- p.57 / Chapter 3.5.1 --- ONE BIT DATA BUS --- p.57 / Chapter 3.5.2 --- EIGHT BITS DATA BUS --- p.59 / Chapter 3.6 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.60 / Chapter 4. --- SIMULATION --- p.63 / Chapter 4.1 --- SIMULATION ENVIRONMENT --- p.64 / Chapter 4.1.1 --- SIMULATION PARAMETERS --- p.64 / Chapter 4.1.2 --- MEMORY TIMING SPECIFICATIONS --- p.64 / Chapter 4.1.3 --- BIT LINE LOAD DETERMINATION --- p.67 / Chapter 4.2 --- BENCHMARK SIMULATION --- p.69 / Chapter 4.2.1 --- CIRCUIT SCHEMATIC --- p.69 / Chapter 4.2.2 --- RESULTS --- p.71 / Chapter 4.3 --- CURRENT SENSING COMPLETION DETECTION --- p.73 / Chapter 4.3.1 --- CIRCUIT SCHEMATIC --- p.73 / Chapter 4.3.2 --- SENSE AMPLIFIER CURRENT CHARACTERISTICS --- p.75 / Chapter 4.3.3 --- RESULTS --- p.76 / Chapter 4.3.4 --- OBSERVATIONS --- p.80 / Chapter 4.4 --- VOLTAGE SENSING COMPLETION DETECTION --- p.82 / Chapter 4.4.1 --- CIRCUIT SCHEMATIC --- p.82 / Chapter 4.4.2 --- RESULTS --- p.83 / Chapter 4.5 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.89 / Chapter 4.5.1 --- CIRCUIT SCHEMATIC --- p.89 / Chapter 4.5.2 --- RESULTS --- p.90 / Chapter 5. --- TESTING --- p.97 / Chapter 5.1 --- TEST CHIP DESIGN --- p.98 / Chapter 5.1.1 --- BLOCK DIAGRAM --- p.98 / Chapter 5.1.2 --- SCHEMATIC --- p.100 / Chapter 5.1.3 --- LAYOUT --- p.102 / Chapter 5.2 --- HSPICE POST-LAYOUT SIMULATION RESULTS --- p.104 / Chapter 5.2.1 --- GRAPHICAL RESULTS --- p.105 / Chapter 5.2.2 --- VOLTAGE SENSING COMPLETION DETECTION --- p.108 / Chapter 5.2.3 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.114 / Chapter 5.3 --- MEASUREMENTS --- p.117 / Chapter 5.3.1 --- LOGIC RESULTS --- p.118 / Chapter 5.3.1.1 --- METHOD --- p.118 / Chapter 5.3.1.2 --- RESULTS --- p.118 / Chapter 5.3.2 --- TIMING RESULTS --- p.119 / Chapter 5.3.2.1 --- METHOD --- p.119 / Chapter 5.3.2.2 --- GRAPHICAL RESULTS --- p.121 / Chapter 5.3.2.3 --- VOLTAGE SENSING COMPLETION DETECTION --- p.123 / Chapter 5.3.2.4 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.125 / Chapter 6. --- DISCUSSION --- p.127 / Chapter 6.1 --- CURRENT SENSING COMPLETION DETECTION --- p.128 / Chapter 6.1.1 --- COMMENTS AND CONCLUSION --- p.128 / Chapter 6.1.2 --- SUGGESTION --- p.128 / Chapter 6.2 --- VOLTAGE SENSING COMPLETION DETECTION --- p.129 / Chapter 6.2.1 --- RESULTS COMPARISON --- p.129 / Chapter 6.2.1.1 --- GENERAL --- p.129 / Chapter 6.2.1.2 --- BIT LINE LOAD --- p.132 / Chapter 6.2.1.3 --- BIT LINE SEGMENTATION --- p.133 / Chapter 6.2.2 --- RESOURCE CONSUMPTION --- p.133 / Chapter 6.2.2.1 --- AREA --- p.133 / Chapter 6.2.2.2 --- POWER --- p.134 / Chapter 6.2.3 --- COMMENTS AND CONCLUSION --- p.134 / Chapter 6.3 --- MULTIPLE DELAY COMPLETION GENERATION --- p.135 / Chapter 6.3.1 --- RESULTS COMPARISON --- p.135 / Chapter 6.3.1.1 --- GENERAL --- p.135 / Chapter 6.3.1.2 --- BIT LINE LOAD --- p.136 / Chapter 6.3.1.3 --- BIT LINE SEGMENTATION --- p.137 / Chapter 6.3.2 --- RESOURCE CONSUMPTION --- p.138 / Chapter 6.3.2.1 --- AREA --- p.138 / Chapter 6.3.2.2 --- POWER --- p.138 / Chapter 6.3.3 --- COMMENTS AND CONCLUSION --- p.138 / Chapter 6.4 --- GENERAL COMMENTS --- p.139 / Chapter 6.4.1 --- COMPARISON OF THE THREE TECHNIQUES --- p.139 / Chapter 6.4.2 --- BIT LINE SEGMENTATION --- p.141 / Chapter 6.5 --- APPLICATION --- p.142 / Chapter 6.6 --- FURTHER DEVELOPMENTS --- p.144 / Chapter 6.6.1 --- INTERACE WITH TWO-PHASE HCP --- p.144 / Chapter 6.6.2 --- DATA BUS EXPANSION --- p.146 / Chapter 6.6.3 --- SPEED OPTIMIZATION --- p.147 / Chapter 6.6.4 --- MODIFIED WRITE COMPLETION METHOD --- p.150 / Chapter 7. --- CONCLUSION --- p.152 / Chapter 7.1 --- PROBLEM DEFINITION --- p.152 / Chapter 7.2 --- IMPLEMENTATION --- p.152 / Chapter 7.3 --- EVALUATION --- p.153 / Chapter 7.4 --- COMMENTS AND SUGGESTIONS --- p.155 / Chapter 8. --- REFERENCES --- p.R-l / Chapter 9. --- APPENDIX --- p.A-l / Chapter 9.1 --- HSPICE SIMULATION PARAMETERS --- p.A-l / Chapter 9.1.1 --- TYPICAL SIMULATION CONDITION --- p.A-l / Chapter 9.1.2 --- FAST SIMULATION CONDITION --- p.A-3 / Chapter 9.1.3 --- SLOW SIMULATION CONDITION --- p.A-4 / Chapter 9.2 --- SRAM CELL LAYOUT AND NETLIST --- p.A-5 / Chapter 9.3 --- TEST CHIP SPECIFICATIONS --- p.A-8 / Chapter 9.3.1 --- GENERAL SPECIFICATIONS --- p.A-8 / Chapter 9.3.2 --- PIN ASSIGNMENT --- p.A-9 / Chapter 9.3.3 --- TIMING DIAGRAMS AND SPECIFICATIONS --- p.A-10 / Chapter 9.3.4 --- SCHEMATICS AND LAYOUTS --- p.A-11 / Chapter 9.3.4.1 --- STANDARD MEMORY COMPONENTS --- p.A-12 / Chapter 9.3.4.2 --- DVSCD AND MDCG COMPONENTS --- p.A-20 / Chapter 9.3.5 --- MICROPHOTOGRAPH --- p.A-25

by Tang Oo. / Thesis submitted in: December 1997. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 68-[75]). / Abstract also in Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- The Concept of Cross-Path Switching --- p.8 / Chapter 1.3 --- Contribution and Organization of Thesis --- p.12 / Chapter 2 --- The Virtual Path Scheduling Scheme --- p.14 / Chapter 2.1 --- The Trade-off Between Throughput and Concentration Loss --- p.14 / Chapter 2.2 --- Partition of Virtual Paths --- p.19 / Chapter 2.3 --- The Capacity and Route Assignment of Virtual Paths --- p.21 / Chapter 3 --- Performance Analysis and Simulation Results --- p.28 / Chapter 3.1 --- The Improvement of Concentration Loss --- p.28 / Chapter 3.2 --- The Throughput with Look-ahead Scheme --- p.30 / Chapter 3.3 --- The Throughput with Input Smoothing Scheme --- p.34 / Chapter 3.4 --- The Throughput with Bursty Source --- p.37 / Chapter 3.5 --- Buffer Dimensioning and The Cell Loss Probability Due to Buffer Overflow --- p.38 / Chapter 4 --- Capacity Assignment and Evaluation of Multiplexing Gain --- p.47 / Chapter 4.1 --- Principle of Capacity Assignment --- p.47 / Chapter 4.2 --- The Model of Virtual Path --- p.49 / Chapter 4.3 --- Capacity Assignment for CBR Service --- p.51 / Chapter 4.4 --- Capacity Assignment for Real-time VBR Service --- p.53 / Chapter 4.5 --- Capacity Assignment for Non Real-time VBR Service --- p.55 / Chapter 4.6 --- Capacity Matrix --- p.56 / Chapter 4.7 --- The Evaluation of Multiplexing Gain of Input Stage --- p.58 / Chapter 5 --- Discussions and Conclusions --- p.64 / Bibliography --- p.67

by Lin Hon Man. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 59-[63]). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Organization of Thesis --- p.3 / Chapter 2 --- Principles of Multicast Cross-Path Switches --- p.4 / Chapter 2.1 --- Introduction --- p.4 / Chapter 2.2 --- Unicast Cross-Path switch --- p.5 / Chapter 2.2.1 --- Routing properties in Clos networks --- p.5 / Chapter 2.2.2 --- Quasi-static routing procedures --- p.5 / Chapter 2.2.3 --- Capacity and Route Assignment --- p.7 / Chapter 2.3 --- Multicast Cross-Path Switch --- p.8 / Chapter 2.3.1 --- Scheme 1 - Cell replication performed at both input and output stages --- p.10 / Chapter 2.3.2 --- Scheme 2 - Cell replication performed only at the input stage --- p.10 / Chapter 3 --- Architectures --- p.14 / Chapter 3.1 --- Introduction --- p.14 / Chapter 3.2 --- Input Module Design (Scheme 1) --- p.16 / Chapter 3.2.1 --- Input Header Translator --- p.16 / Chapter 3.2.2 --- Input Module Controller --- p.17 / Chapter 3.2.3 --- Input Replication Network (Scheme 1) --- p.19 / Chapter 3.2.4 --- Routing Network --- p.23 / Chapter 3.3 --- Central Modules --- p.24 / Chapter 3.4 --- Output Module Design (Scheme 1) --- p.24 / Chapter 3.5 --- Input Module Design (Scheme 2) --- p.25 / Chapter 3.5.1 --- Input Header Translator (Scheme 2) --- p.26 / Chapter 3.5.2 --- Input Module Controller (Scheme 2) --- p.27 / Chapter 3.5.3 --- Input Replication Network (Scheme 2) --- p.28 / Chapter 3.6 --- Output Module Design (Scheme 2) --- p.29 / Chapter 4 --- Performance Evaluations --- p.31 / Chapter 4.1 --- Introduction --- p.31 / Chapter 4.2 --- Traffic characteristics --- p.31 / Chapter 4.2.1 --- Fanout distribution --- p.31 / Chapter 4.2.2 --- Middle stage traffic load and its calculation --- p.32 / Chapter 4.3 --- Throughput Performance --- p.34 / Chapter 4.4 --- Delay Performance --- p.37 / Chapter 4.4.1 --- Input Stage Delay --- p.38 / Chapter 4.4.2 --- Output Stage Delay --- p.39 / Chapter 4.5 --- Cell Loss Performance --- p.43 / Chapter 4.5.1 --- Cell Loss due to Buffer Overflow --- p.44 / Chapter 4.5.2 --- Cell Loss Due to Output Contention --- p.45 / Chapter 4.6 --- Complexities --- p.50 / Chapter 5 --- Conclusions --- p.57 / Bibliography --- p.59

by Jin Mai. / Thesis submitted in: June 1998. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1999. / Includes bibliographical references (leaves 62-[67]). / Abstract also in Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background and Motivation --- p.1 / Chapter 1.2 --- Organization of the thesis --- p.8 / Chapter 2 --- Principles of WDM Cross-Path Switch --- p.11 / Chapter 2.1 --- Principles of path scheduling --- p.11 / Chapter 2.2 --- Call setup and path rearrangement --- p.15 / Chapter 2.3 --- ABR control --- p.17 / Chapter 3 --- Star coupler and WDM path scheduling --- p.20 / Chapter 3.1 --- Star coupler and other WDM ATM switches --- p.20 / Chapter 3.2 --- Two schemes of implementation --- p.22 / Chapter 4 --- input/output modules and local routing --- p.26 / Chapter 4.1 --- Shared buffer memory switch --- p.26 / Chapter 4.2 --- local routing at input/output modules --- p.29 / Chapter 5 --- Multicasting --- p.32 / Chapter 5.1 --- Two multicasting schemes --- p.32 / Chapter 5.2 --- Call blocking --- p.36 / Chapter 6 --- Performance --- p.37 / Chapter 6.1 --- Introduction --- p.37 / Chapter 6.2 --- Switch complexity --- p.38 / Chapter 6.3 --- Speed up --- p.40 / Chapter 6.4 --- Two multicasting schemes --- p.41 / Chapter 7 --- Switch Model and Operation --- p.47 / Chapter 8 --- Conclusions --- p.50 / Chapter A --- Effective bandwidth and QoS guarantee --- p.52 / Chapter A.l --- ATM service categories and QoS parameters --- p.52 / Chapter A.2 --- Effective bandwidth for single source --- p.53 / Chapter A.2.1 --- Markovian on/off source approach --- p.54 / Chapter A.2.2 --- Leaky bucket regulated source --- p.55 / Chapter A.3 --- Effective bandwidth for multiplexed sources --- p.60 / Chapter A.3.1 --- Gaussian model approach --- p.60 / Bibliography --- p.62

by Ding Quan-Long. / Thesis (Ph.D.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (p. 135-141). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web.

by Cheuk-hung Lam. / Thesis (Ph.D.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (p. 120-[129]). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web.

by Yee Ka Chi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (leaves 101-[106]). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.1.1 --- Large Scale Switch Interconnections --- p.2 / Chapter 1.1.2 --- Multichannel Switching and Resequencing --- p.6 / Chapter 1.1.3 --- Scheduling --- p.7 / Chapter 2 --- Hierarchical Banyan Switch Interconnection --- p.12 / Chapter 2.1 --- Introduction --- p.12 / Chapter 2.2 --- Switch Architecture --- p.13 / Chapter 2.3 --- Switch Operation --- p.19 / Chapter 2.3.1 --- Call Setup --- p.19 / Chapter 2.3.2 --- Cell Routing --- p.21 / Chapter 2.3.3 --- Fault Tolerance --- p.27 / Chapter 2.4 --- Call Blocking Analysis --- p.28 / Chapter 2.4.1 --- Dilated Banyan --- p.29 / Chapter 2.4.2 --- Dilated Benes Network --- p.30 / Chapter 2.4.3 --- HBSI --- p.30 / Chapter 2.5 --- Results and Discussions --- p.31 / Chapter 2.6 --- Summary --- p.37 / Chapter 3 --- Multichannel Switching and Resequencing --- p.40 / Chapter 3.1 --- Introduction --- p.40 / Chapter 3.2 --- Channel Assignment --- p.41 / Chapter 3.2.1 --- VC-Based Channel Allocation Mechanism --- p.41 / Chapter 3.2.2 --- Port-Based Channel Allocation Mechanism --- p.45 / Chapter 3.2.3 --- Trunk-Based Channel Allocation Mechanism --- p.46 / Chapter 3.3 --- Resequencer --- p.50 / Chapter 3.3.1 --- Resequencing Algorithm --- p.50 / Chapter 3.4 --- Results and Discussion --- p.55 / Chapter 3.5 --- Summary --- p.60 / Chapter 4 --- Scheduling --- p.62 / Chapter 4.1 --- Introduction --- p.62 / Chapter 4.2 --- Virtual Clock Scheduling (VCS) --- p.62 / Chapter 4.3 --- Gated Virtual Clock Scheduling (GVCS) --- p.70 / Chapter 4.4 --- Time-Priority Model --- p.75 / Chapter 4.5 --- Programmable Rate-based Scheduler (PRS) --- p.80 / Chapter 4.6 --- Integration with Resequencer --- p.83 / Chapter 4.7 --- Results and Discussions --- p.86 / Chapter 4.8 --- Summary --- p.96 / Chapter 5 --- Conclusion --- p.99 / Bibliography --- p.101

by Ngai Li. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (leaves 66-69). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Video Compression and Transport --- p.2 / Chapter 1.2 --- Research Contributions --- p.6 / Chapter 1.2.1 --- Joint Rate Control of VBR Encoded Video --- p.6 / Chapter 1.2.2 --- Transporting VBR Video on LB Controlled Channel --- p.7 / Chapter 1.3 --- Organization of Thesis --- p.7 / Chapter 2 --- Preliminary --- p.9 / Chapter 2.1 --- Statistical Characteristics of MPEG-1 Encoded Video --- p.9 / Chapter 2.2 --- Temporal and Spatial Smoothing --- p.14 / Chapter 2.2.1 --- Temporal Smoothing --- p.14 / Chapter 2.2.2 --- Spatial Smoothing --- p.15 / Chapter 2.3 --- A Single Source Control-Theoretic Framework for VBR-to-CBR Video Adaptation --- p.16 / Chapter 3 --- Joint Rate Control of VBR Encoded Video --- p.19 / Chapter 3.1 --- Analytical Models --- p.21 / Chapter 3.2 --- Analysis --- p.27 / Chapter 3.2.1 --- Stable Region --- p.29 / Chapter 3.2.2 --- Final Value of the State Variables --- p.33 / Chapter 3.2.3 --- Peak Values of Buffer-occupancy Deviation and Image- quality Fluctuation --- p.35 / Chapter 3.2.4 --- SAE of Buffer-occupancy Deviation and Image-quality Fluc- tuation --- p.42 / Chapter 3.3 --- Experimental Results --- p.43 / Chapter 3.4 --- Concluding Remarks --- p.48 / Chapter 4 --- Transporting VBR Video on LB Controlled Channel --- p.50 / Chapter 4.1 --- Leaky Bucket Access Control --- p.51 / Chapter 4.2 --- Greedy Token-usage Strategy --- p.53 / Chapter 4.3 --- Non-greedy Token-usage Strategy --- p.57 / Chapter 4.4 --- Concluding Remarks --- p.60 / Chapter 5 --- Conclusions --- p.62 / Chapter 5.1 --- Joint Rate Control of Multiple VBR Videos --- p.62 / Chapter 5.2 --- LB Video Compression --- p.63 / Chapter 5.3 --- Further Study --- p.64 / Chapter 5.4 --- Publications --- p.65 / Bibliography --- p.65

The majority of ATM switches that have been proposed only support unicast (point-to-point) connections. Those supporting multicast (point-to-multipoint) connections tend to perform poorly, with acceptable multicast performance only achievable using an excessive amount of hardware. Because of the growing importance of multicast traffic, there is the demand for multicast switch designs which offer both low hardware complexity and high performance. This research investigates a class of multicast ATM switches called recycling switches which can satisfy both requirements. Recycling switch performance is studied using a simulated network model. The major performance parameters measured are the loss rate, mean delay, and delay variance of cells crossing through the switch under uniform and bursty traffic patterns. The reason recycling is not more widely used in multicast switches is the perception that it can lead to some multicast cells receiving lower quality of service than others. This research demonstrates a new priority-based approach to designing recycling multicast ATM switches which addresses this problem while maintaining low complexity and excellent scalability. / Masters Thesis