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Condition-based maintenance of actuator systems using a model-based approach /Vasquez Arvallo, Agustin, January 2000 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 293-300). Available also in a digital version from Dissertation Abstracts.
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Hierarchical sequential test generation for large circuits /Tupuri, Raghuram Srinivasa. January 1999 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 1999. / Includes bibliographical references (leaves 108-118). Available also in a digital version from Dissertation Abstracts.
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Optimal design of VLSI structures with built-in self test based on reduced pseudo-exhaustive testingPimenta, Tales Cleber. January 1992 (has links)
Thesis (Ph. D.)--Ohio University, November, 1992. / Title from PDF t.p.
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Hierarchical sequential test generation for large circuits /Tupuri, Raghuram Srinivasa, January 1999 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 108-118). Available also in a digital version from Dissertation Abstracts.
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A case study in automated testing /Daigneault, Thomas E. January 1993 (has links)
Report (M.S.)--Virginia Polytechnic Institute and State University. M.S. 1993. / Abstract. Includes bibliographical references (leaf 107). Also available via the Internet.
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Built-in self-test design optimization for scan-based circuitsZhang, Sheng. January 1900 (has links)
Thesis (Ph.D.)--University of Nebraska-Lincoln, 2006. / Title from title screen (site viewed May 23, 2007). PDF text: vi, 140 p. : ill. (some col.) ; 2.70Mb UMI publication number: AAT 3236905. Includes bibliographical references. Also available in microfilm and microfiche formats.
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Merging concurrent checking and off-line BISTSun, Xiaoling 05 July 2018 (has links)
This dissertation encompasses primarily design for testability (DFT) problems of concurrent checking and structural off-line Built-In Self-Test. We present a new DFT method, which employs cyclic code checking as a medium to combine the concurrent checking and signature analysis in a built-in fashion.
It uses bit-sliced linear feedback shift registers (LFSRs) or linear cellular automata registers (LCARs) as the implementation mechanism. A circuit under test designed in this method supports both on-line and off-line testability with shared hardware resources. It has comparable on-line error-detecting ability to the conventional error-detecting codes and without affecting the high fault coverage of off-line signature analysis. This testing scheme complies with the IEEE boundary-scan standard and is applicable to general circuitry.
Evaluations of the proposed scheme are carried out with respect to the area overhead, performance and testing time, design complexity, pin count, and fault coverage.
The concatenation properties of LCARs are introduced and recent developments
in related issues are reviewed. Finally, a new area estimation method for circuit
design is presented to ease silicon cost measurement / Graduate
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Built-in performance characterization of embedded mixed-signal circuitsShin, Hongjoong, January 1900 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.
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Synthesis of testable core-based designs /Pouya, Bahram, January 2000 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 94-100). Available also in a digital version from Dissertation Abstracts.
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Built-in performance characterization of embedded mixed-signal circuitsShin, Hongjoong 28 August 2008 (has links)
Not available
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