Based on different sampling theorem, for example classic Shannon’s sampling theorem and Papoulis’ generalized sampling theorem, signals are processed by the sampling devices without loss of information. As an interface between radio receiver front-ends and digital signal processing blocks, sampling devices play a dominant role in digital radio communications. Under the concept of Software Defined Radio (SDR), radio systems are going through the second evolution that mixes analog, digital and software technologies in modern radio designs. One design goal of SDR is to put the A/D converter as close as possible to the antenna. BandPass Sampling (BPS) enables one to have an interface between the RF or the higher IF signal and the A/D converter, and it might be a solution to SDR. However, three sources of performance degradation present in BPS systems, harmful signal spectral overlapping, noise aliasing and sampling timing jitter, hinder the conventional BPS theory from practical circuit implementations. In this thesis work, Generalized Quadrature BandPass Sampling (GQBPS) is first invented and comprehensively studied with focus on the noise aliasing problem. GQBPS consists of both BPS and FIR filtering that can use either real or complex coefficients. By well-designed FIR filtering, GQBPS can also perform frequency down-conversion in addition to noise aliasing reduction. GQBPS is a nonuniform sampling method in most cases. With respect to real circuit implementations, uniform sampling is easier to be realized compared to nonuniform sampling. GQBPS has been also extended to Generalized Uniform BandPass Sampling (GUBPS). GUBPS shares the same property of noise aliasing suppression as GQBPS besides that the samples are uniformly spaced. Due to the moving average operation of FIR filtering, the effect of sampling jitter is also reduced to a certain degree in GQBPS and GUBPS. By choosing a suitable sampling rate, harmful signal spectral overlapping can be avoided. Due to the property of quadrature sampling, the “self image” problem caused by I/Q mismatches is eliminated. Comprehensive theoretical analyses and program simulations on GQBPS and GUBPS have been done based on a general mathematic model. Circuit architecture to implementing GUBPS in Switched-Capacitor circuit technique has been proposed and analyzed. To improve the selectivity at the sampling output, FIR filtering is extended by adding a 1st order complex IIR filter in the implementation. GQBPS and GUBPS operate in voltage-mode. Besides voltage sampling, BPS can also be realized by charge sampling in current-mode. Most other research groups in this area are focusing on bandpass charge sampling. However, the theoretical analysis shows that our GQBPS and GUBPS in voltage mode are more efficient to suppress noise aliasing as compared to bandpass charge sampling with embedded filtering. The aliasing bands of sampled-data spectrum are always weighted by continuous-frequency factors for bandpass charge sampling with embedded filtering while discrete-frequency factors for GQBPS and GUBPS. The transmission zeros of intrinsic filtering will eliminate the corresponding whole aliasing bands of both signal and noise in GQBPS and GUBPS, while it will only cause notches at a limited set of frequencies in bandpass charge sampling. In addition, charge sampling performs an intrinsic continuous-time sinc function that always includes lowpass filtering. This is a drawback for a bandpass input signal. / QC 20100921

Les nouveaux besoins en communications sans fil pussent le développement de systèmes de transmission RF en termes the reconfigurabilité, multistandard et à basse consommation. Ces travaux de thèse font l’objet de la proposition d’une nouvelle architecture de réception capable d’adresser ces aspects dans le contexte des réseaux WPAN. La technique de sous échantillonnage (BPS-Bandpass Sampling) est appliquée et permet d’exploiter et certain nombre d’avantages liées au traitement du signal à Temps Discret (DT-Discrete Time signal processing), notamment le filtrage et la décimation. Si comparées à la Radio Logicielle, ces techniques permettent de relâcher les contraintes liées aux ADCs en maintenant des caractéristiques multistandard et de reconfigurabilité. Un simulateur dans le domaine fréquentiel large bande a été développé sous MATLAB pour répondre à des limitations au niveau système comme par exemple le repliement spectral et le produit gain bande. En addition avec une nouvelle méthode de conception système, cet outil permet de séparer les différentes contraintes des blocs pour la définition d’un plan de fréquence et the filtrage optimaux. La séparation des différentes contributions dans la dégradation du SNDR (notamment le bruit thermique, bruit de phase, non linéarité et le repliement), permet de relâcher de spécifications critiques liées à la consommation de puissance. L’architecture à sous échantillonnage proposée dans la thèse est résultat d’une comparaison quantitative des différentes architectures à sous échantillonnage, tout en appliquant la méthode et l’outil de conception système développés. Des aspects comme l’optimisation du filtrage entre les techniques à temps continu et temps discret et le plan de fréquence associé, permettent de trouve l’architecture qui représente le meilleur compromis entre la consommation électrique et l’agilité, dans le contexte voulu. Le bloc de filtrage à temps discret est identifié comme étant critique, et une étude sur les limitations d’implémentation circuit est menée. Des effets come les capacités parasites, l’imparité entre les capacités, le bruit du commutateur, la non linéarité, le gain finit de Ampli OP, sont évalués à travers d’une simulation comportementale en VHDL-AMS. On observe la robustesse des circuits orientés temps discret par rapport les contraintes des nouvelles technologies intégrés. Finalement, le système est spécifié en termes de bruit de phase, qui peuvent représenter jusqu’à 30% de la consommation en puissance. Dans ce but, une nouvelle méthode numérique est proposée pour être capable d’évaluer le rapport signal sur distorsion due au jitter SDjR dans le processus de sous échantillonnage. En plus, une conclusion non intuitive est survenue de cette étude, où on que réduire la fréquence d’échantillonnage n’augmente pas les contraintes en termes de jitter pour le système. L’architecture proposée issue de cette étude est sujet d’un développement circuit pour la validation du concept. / New needs on wireless communications pushes the development in terms reconfigurable, multistandards and low power radio systems. The objective of this work is to propose and design new receiver architecture capable of addressing these aspects in the context of the WPAN networks. The technique of Bandpass Sampling (BPS) is applied and permits to exploit a certain number of advantages linked to the discrete time (DT) signal processing, notably filtering and decimation. Compared to the Software-defined Radio (SDR), these techniques permit to relax the ADC constraints while keeping the multi standard and reconfigurable features. A wide band system level simulation tool is developed using MATLAB platform to overcome system level limitations such spectral aliasing and gain bandwidth product. In addition to a new system design method, the tool helps separating the blocks constraints and defining the optimum frequency plan and filtering. Separating the different contributions on the SNDR degradation (noise, phase noise, non linearity, and aliasing), critical specifications for power consumption can be relaxed. The proposed BPS architecture on the thesis is a result of a quantitative comparison of different BPS architectures, applying the system design method and tool. Aspects such filtering optimization between continuous and discrete time filtering and the associated frequency plan permitted to find the architecture which represents the best trade-off between power consumption and agility on the aimed context. The DT filtering block is therefore identified as critical block, which a study on the circuit implementation limitations is carried out. Effects such parasitic capacitances and capacitance mismatch, switch noise, non linear distortion, finite gain OTA, are evaluated through VHDL-AMS modelling. It is observed the robustness of discrete time oriented circuits. Finally, phase noise specifications are given considering that frequency synthesis circuits may represent up to 30% of the power consumption. For that goal, a new numerical method is proposed, capable of evaluating the signal to jitter distortion ratio SDjR on the BPS process. Moreover, a non intuitive conclusion is given, where reducing the sampling frequency does not increase the constraints in terms of jitter. The proposed architecture issue from this study is in stage of circuit level design in the project team of LETI for final proof of concept.