The object of this thesis is to explore the low-frequency noise (LFN) in silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) and lateral bipolar junction transistors (BJTs). The LFN of SiGe HBTs and lateral BJTs not only determines the lowest detectable signal limit but also induces phase noise in high-frequency applications. Characterizing the LFN behavior and understanding the physical noise mechanism, therefore, are very important to improve the device and circuit performance. The dissertation achieves the object by investigating the LFN of SiGe HBTs and lateral BJTs with different structures for performance optimization and radiation tolerance, as well as by building models that explain the physical mechanism of LFN in these advance bipolar technologies. The scope of this research is separated into two main parts: the LFN of SiGe HBTs; and the LFN of lateral BJTs. The research in the LFN of SiGe HBTs includes investigating the effects of interfacial oxide (IFO), temperature, geometrical dimensions, and proton radiation. It also includes utilizing physical models to probe noise mechanisms. The research in the LFN of lateral BJTs includes exploring the effects of doping and geometrical dimensions. The research work is envisioned to enhance the understanding of LFN in SiGe HBTs and lateral BJTs.

Two MOS-Bipolar composite power semiconductor switching devices are proposed and experimentally demonstrated. These devices feature high voltage and high current capabilities, fast switching speeds, simple gate drive requirements, savings in chip area, reverse bias second breakdown ruggedness and large safe operating areas. Application characteristics of the devices for high frequency power inverter circuits are discussed. Monolithic integration of the two composite devices are also proposed. / Ph. D.

In this doctoral dissertation, the author presents the theoretical foundation, the analysis and design of analog and RF circuits, the chip level implementation, and the experimental validation pertaining to a new radio frequency integrated circuit (RFIC) power amplifier (PA) architecture that is intended for wireless portable transceivers. / A method called Gated Envelope Feedback is proposed to allow the automatic hardware reconfiguration of a stand-alone RFIC PA in multiple states for power efficiency improvement purposes. The method uses self-operating and fully integrated circuitry comprising RF power detection, switching and sequential logic, and RF envelope feedback in conjunction with a hardware gating function for triggering and activating current reduction mechanisms as a function of the transmitted RF power level. Because of the critical role that RFIC PA components occupy in modern wireless transceivers, and given the major impact that these components have on the overall RF performances and energy consumption in wireless transceivers, very significant benefits stem from the underlying innovations. / The method has been validated through the successful design of a 1.88GHz COMA RFIC PA with automatic hardware reconfiguration capability, using an industry renowned state-of-the-art GaAs HBT semiconductor process developed and owned by Skyworks Solutions, Inc., USA. The circuit techniques that have enabled the successful and full on-chip embodiment of the technique are analyzed in details. The IC implementation is discussed, and experimental results showing significant current reduction upon automatic hardware reconfiguration, gain regulation performances, and compliance with the stringent linearity requirements for COMA transmission demonstrate that the gated envelope feedback method is a viable and promising approach to automatic hardware reconfiguration of RFIC PA's for current reduction purposes. Moreover, in regard to on-chip integration of advanced PA control functions, it is demonstrated that the method is better positioning GaAs HBT technologies, which are known to offer very competitive RF performances but inherently have limited integration capabilities. / Finally, an analytical approach for the evaluation of inter-modulation distortion (IMD) in envelope feedback architectures is introduced, and the proposed design equations and methodology for IMD analysis may prove very helpful for theoretical analyses, for simulation tasks, and for experimental work.

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