With the advancement of display technology, consumers expect high quality display of image and video data. Many viewers are used to watching video content on high definition television and large screens. However, certain display technologies, such as several of those used in portable electronic books, are limited on resources such as the availability of number of bits per pixel (i.e. the bit-depth). Display of good or even acceptable perceptual quality video on these devices is a hard technical problem that a display designer must solve. Video halftoning reduces the number of represented colors or gray levels for display on devices that are unable to render the video at full bit-depth. Bit-depth reduction results in visible spatial and temporal artifacts. The designer would want to choose the halftoning algorithm that reduces these artifacts while meeting the target platform constraints. These constraints include available bit-depth, spatial resolution, computational power, and desired frame rate. Perceptual quality assessment techniques are useful in comparing different video halftoning algorithms that satisfy the constraints. This dissertation develops a framework for the evaluation of two key temporal artifacts, flicker and dirty-window-effect, in medium frame rate binary video halftones generated from grayscale continuous-tone videos. The possible causes underlying these temporal artifacts are discussed. The framework is based on perceptual criteria and incorporates properties of the human visual system. The framework allows for independent assessment of each of the temporal artifacts. This dissertation presents design of algorithms that generate medium frame rate binary halftone videos. The design of the presented video halftone generation algorithms benefits from the proposed temporal artifact evaluation framework and is geared towards reducing the visibility of temporal artifacts in the generated medium frame rate binary halftone videos. This dissertation compares the relative power consumption associated with several medium frame rate binary halftone videos generated using different video halftone generation algorithms. The presented power performance analysis is generally applicable to bistable display devices. This dissertation develops algorithms to enhance medium frame rate binary halftone videos by reducing flicker. The designed enhancement algorithms reduce flicker while attempting to constrain any resulting increase in perceptual degradation of the spatial quality of the halftone frames. This dissertation develops algorithms to enhance medium frame rate binary halftone videos by reducing dirty-window-effect. The enhancement algorithms reduce dirty-window-effect while attempting to constrain any resulting increase in perceptual degradation of the spatial quality of the halftone frames. Finally, this dissertation proposes design of medium frame rate binary halftone video enhancement algorithms that attempt to reduce a temporal artifact, flicker or dirty-window-effect, under both spatial and temporal quality constraints. Temporal quality control is incorporated by using the temporal artifact assessment framework developed in this dissertation. The incorporation of temporal quality control, in the process of reducing flicker or dirty-window-effect, helps establish a balance between the two temporal artifacts in the enhanced video. At the same time, the spatial quality control attempts to constrain any increase in perceptual degradation of the spatial quality of the enhanced halftone frames. / text

The compressive sensing (CS) framework aims to ease the burden on analog-to-digital converters (ADCs) by exploiting inherent structure in natural and man-made signals. It has been demonstrated that structured signals can be acquired with just a small number of linear measurements, on the order of the signal complexity. In practice, this enables lower sampling rates that can be more easily achieved by current hardware designs. The primary bottleneck that limits ADC sampling rates is quantization, i.e., higher bit-depths impose lower sampling rates. Thus, the decreased sampling rates of CS ADCs accommodate the otherwise limiting quantizer of conventional ADCs. In this thesis, we consider a different approach to CS ADC by shifting towards lower quantizer bit-depths rather than lower sampling rates. We explore the extreme case where each measurement is quantized to just one bit, representing its sign. We develop a new theoretical framework to analyze this extreme case and develop new algorithms for signal reconstruction from such coarsely quantized measurements. The 1-bit CS framework leads us to scenarios where it may be more appropriate to reduce bit-depth instead of sampling rate. We find that there exist two distinct regimes of operation that correspond to high/low signal-to-noise ratio (SNR). In the measurement compression (MC) regime, a high SNR favors acquiring fewer measurements with more bits per measurement (as in conventional CS); in the quantization compression (QC) regime, a low SNR favors acquiring more measurements with fewer bits per measurement (as in this thesis). A surprise from our analysis and experiments is that in many practical applications it is better to operate in the QC regime, even acquiring as few as 1 bit per measurement. The above philosophy extends further to practical CS ADC system designs. We propose two new CS architectures, one of which takes advantage of the fact that the sampling and quantization operations are performed by two different hardware components. The former can be employed at high rates with minimal costs while the latter cannot. Thus, we develop a system that discretizes in time, performs CS preconditioning techniques, and then quantizes at a low rate.