Thesis (Ph. D.)--University of Wisconsin--Madison, 1957. / Typescript. Vita. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves [98]-100).

M.Ing. / The drive for smaller and higher density power supplies have been realised by advances in switching technologies, higher frequencies and smaller components. Along with the advances of higher switching frequencies, came a number of restrictive parasitic effects that were insignificant at lower frequencies (in use a few years ago). A problem that is becoming of increasing concern, as the frequencies increase, rise times decrease and current levels increase, is the reactance of the parasitic inductance in voltage fed converter. This inductance is responsible for a multitude of limitations and problems in high frequency converters, with the most important being unstable voltage supplies, large voltage spikes during switching (which leads to electromagnetic interference), and power transfer limitations. The main contributors of this parasitic inductance was found to be the inherent inductance of the conductors of the DC bus, the internal inductance of the capacitor elements used in the DC bus and the paralleling of these capacitor elements (capacitor bank). It was decided to investigate the cause of these identified inductances in an attempt at finding a means to reduce them, thereby improving the performance of the converter. This was accompanied by a search into prediction methods for the inductance and capacitance of the DC bus conductors. The ability to predict the inductance and capacitance inherent to the DC bus conductors, will allow for a large decrease in prototyping, and should give insight into the causes of these elements and how to manipulate them. This was done for the DC bus conductors, and led to insight into their inductance and capacitance origins. Means to reduce this inductance was found, along with the ability to predict the inductance and capacitance of a number of DC bus conductors. The last two identified parasitic inductance sources, the internal inductance of the capacitors and inductance of the capacitor bank, were then investigated. The cause of the inductance in the capacitor elements was discovered, along with the factors on which the capacitor elements are dependent. A great deal of the inductance, and its associated effects, can be avoided through proper capacitor selection and correct capacitor bank design. In order to bring this study in context with a practical scenario, the information previously obtained was incorporated in a full bridge voltage fed converter. The previous findings on inductance and capacitance held equally well when applied to a practical scenario. Additional means to reduce the effects of the parasitic inductances were discovered, and the inductance and capacitance prediction methods proved to be relatively accurate when applied to the DC bus conductors of a physical converter.

Thesis (M.S.)--University of Wisconsin--Madison, 1969. / Vol. 2 mainly program printouts. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references.

Microprocessor-based systems are used for a variety of applications, ranging from industrial control systems to spaceborne systems. The complex nature of tasks to be performed has led to division and distribution of work among different subsystems. A fast and reliable means of information and data transmission among these subsystems is provided by parallel communication busses. Satellite-based systems are susceptible to transient faults caused by cosmic radiation or alpha particles. In order for a system to be usable in such an environment, it must be designed to be upset tolerant. Functionality of the design must be intact in the presence of transient faults. Several standardized bus architectures have been configured to meet a given set of performance specifications. One such bus architecture called the Nubus is used as the basis for the design and development of an upset tolerant bus architecture. The modified structure is called NuFTbus for Nu Fault-Tolerant bus. Rationale for the NuFTbus specification is presented in this thesis. A design of an IC-based bus interface unit is developed. The design is specified in the VHSIC Hardware Description Language (VHDL) and VHDL tools are used to simulate the system behavior. Simulation results are presented. The VHDL circuit description is converted to a gate array layout ready For Fabrication in an appropriate radiation-hardened gate array technology. A description oF the hardware Functional testing Facilities, along with a description of a set of test procedures, is given. / Master of Science

Thesis (M.S.)--Ohio University, November, 1987. / Title from PDF t.p.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004. / Includes bibliographical references (leaves 73-76). Also available in electronic version. Access restricted to campus users.

This document explains the design of the microcontroller based Intelligent Communication Controller (ICC) for the Motorola VMEbus. The card transmits and receives serial data on T1 medium at a rate of 1.544 Mbits/sec. This ICC card is a part of the communication system used in a current differential protection scheme for power distribution systems. / Master of Science

Typescript (photocopy). / Digitized by Kansas Correctional Industries / Department: Electrical and Computer Engineering.

Cheung, Cheuk Kit. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references. / Abstract also in Chinese. / Abstract --- p.1 / 摘要 --- p.2 / Acknowledgements --- p.3 / Table of Contents --- p.4 / List of Figures --- p.9 / Chapter 1. --- Introduction --- p.12 / Chapter 1.1. --- Research Motivation --- p.12 / Chapter 1.1.1. --- Global and Intermediate Interconnects --- p.12 / Chapter 1.1.2. --- Constraints of Repeater Insertion Techniques --- p.13 / Chapter 1.2. --- Research Objective --- p.13 / Chapter 1.3. --- Reference --- p.14 / Chapter 2. --- Voltage Mode and Current Mode Circuits --- p.16 / Chapter 2.1. --- Introduction --- p.16 / Chapter 2.2. --- Voltage Mode Circuit --- p.16 / Chapter 2.3. --- Current Mode Circuit --- p.18 / Chapter 2.4. --- Power Consumption --- p.19 / Chapter 2.5. --- Latency --- p.20 / Chapter 2.6. --- Summary --- p.20 / Chapter 3. --- Transmitter Design --- p.22 / Chapter 3.1. --- Introduction --- p.22 / Chapter 3.2. --- Multi-level Signaling --- p.22 / Chapter 3.3. --- Gated Current Mirror --- p.23 / Chapter 3.4. --- Power Consumption --- p.24 / Chapter 3.5. --- Summary --- p.24 / Chapter 3.6. --- Reference --- p.25 / Chapter 4. --- Receiver Design --- p.26 / Chapter 4.1. --- Introduction --- p.26 / Chapter 4.2. --- Conventional Latched-typed Sense Amplifier --- p.27 / Chapter 4.3. --- Sense Amplifier with Isolated Differential Pair --- p.29 / Chapter 4.4. --- "Power Consumption, Latency and Kick-back Noise Comparison between Different Designs" --- p.30 / Chapter 4.4.1. --- Comparison on Power Consumption --- p.30 / Chapter 4.4.2. --- Comparison on Latency --- p.31 / Chapter 4.4.3. --- Comparison on Kick-back Noise --- p.33 / Chapter 4.5. --- Summary --- p.34 / Chapter 4.6. --- Reference --- p.34 / Chapter 5. --- Inverter Chain --- p.36 / Chapter 5.1. --- Introduction --- p.36 / Chapter 5.2. --- Inverter Chain Based --- p.36 / Chapter 5.3. --- Summary --- p.38 / Chapter 5.4. --- References --- p.38 / Chapter 6. --- Layout Techniques --- p.39 / Chapter 6.1. --- Introduction --- p.39 / Chapter 6.2. --- Two-Dimensional Common Centroid Layout Technique --- p.39 / Chapter 6.3. --- Dummy Devices --- p.40 / Chapter 6.4. --- Summary --- p.42 / Chapter 6.5. --- References --- p.42 / Chapter 7. --- Simulation Results --- p.43 / Chapter 7.1. --- Introduction --- p.43 / Chapter 7.2. --- Simulation of Different Aspect Ratios of Differential Pair --- p.43 / Chapter 7.3. --- System Level Simulation with Different Sense-amplifiers --- p.46 / Chapter 7.4. --- System Level Simulation at Different Data Rate --- p.47 / Chapter 7.5. --- Summary --- p.49 / Chapter 8. --- Measurement Results --- p.50 / Chapter 8.1. --- Introduction --- p.50 / Chapter 8.2. --- Experimental Setup --- p.50 / Chapter 8.2.1. --- Testing Chips --- p.50 / Chapter 8.2.2. --- Equipments Setup --- p.52 / Chapter 8.3. --- Measurement Results --- p.53 / Chapter 8.4. --- Summary --- p.56 / Chapter 9. --- Conclusion --- p.57 / Chapter 9.1. --- Author´ةs Contributions --- p.57 / Chapter 9.2. --- Future Works --- p.58 / Chapter 10. --- Appendix --- p.59

A thesis submitted to the Faculty of Engineering at the University of the Witwatersrand, Johannesburg, in fulfilment of the requirements for the degree of Doctor of Philosophy. / Particularly at the higher system voltages, certain faults have been attributed to VFTs. This work presents a full frequency domain mathematical model of the effects likely to be introduced by the application of a thin ferromagnetic coating to the surfaces of the busbars as a means of attenuating these transients. Experimental verification shows the model to perform accurately as an analysis tool for a continuous coated co-axial system. While comparison between the model developed here (based on a planar conductor) and the very accurate Bessel function solution is presented, it must be remembered that it is not feasible to include the effects of coatings in the latter solution. Hence it is used merely as a bench-mark for improvements to the general model. Consideration is also given to the transient skin effect, and this is shown to result in an increased attenuation of VFTs. detectable during high voltage experimentation. The frequency domain model is extended to that of a full travelling wave model for VFTs in GIS. The Fourier technique is used to move between the frequency and time domains. Laboratory results obtained at high voltage.show that this technique will introduce both risetime increase and peak magnitude attenuation of VFTs. As the most frequent faults directly attributable to disconnector operation are known to be faults to earth at the switch, it is noted that the technique proposed in this work is uniquely suited for use in a design strategy that requires totally robust disconnectors at the expense of more severe VFTs in the GIS. The model is used to determine a range of physical characteristics of materials suitable for use in this application. While the characteristics of the most suitable materials have therefore been established, it is concluded that extensive metallurgical experimentation remains before this technique may be economically applied. / Andrew Chakane 2018