One technique that is used to reduce the errors brought upon signals, when transmitted over noisy channels, is error control coding. One type of such coding, which has a good performance, is turbo coding. In some of the TMS320C64xTM digital signal processors there is a built in coprocessor that performs turbo decoding. This thesis is performed on the account of Communication Developments, within Saab AB and presents an evaluation of this coprocessor. The evaluation deals with both the memory consumption as well as the data rate. The result is also compared to an implementation of turbo coding that does not use the coprocessor. / En teknik som används för att minska de fel som en signal utsätts för vid transmission över en brusig kanal är felrättande kodning. Ett exempel på sådan kodning som ger ett mycket bra resultat är turbokodning. I några digitalsignalprocessorer, av sorten TMS320C64xTM, finns en inbyggd coprocessor som utför turboavkodning. Denna uppsats är utförd åt Communication Development inom Saab AB och presenterar en utvärdering av denna coprocessor. Utvärderingen avser såväl minnesförbrukning som datatakt och innehåller även en jämförelse med en implementering av turbokodning utan att använda coprocessorn.

Modern devices provide a multitude of services that use radio frequencies in continual smaller packages. This size leads to an antenna used to transmit and receive information being usually very inefficient and a lot of power is wasted just to be able to transmit a signal. To mitigate this problem a new antenna was introduced by Dr. Manteghi that is capable of working efficiently across a large band. The antenna achieves this large band by doing quick frequency hopping across multiple channels. In order to test the performance of this antenna against more common antennas, a software radio was needed, such that tested antennas can be analyzed using multiple modulations. This paper presents a software defined radio system that was designed for the purpose of testing the bit-error rate of digital modulations schemes using described and other antennas. The designed system consists of a DSP, an FPGA, and commercially available modules. The combination allows the system to be flexible with high performance, while being affordable. Commercial modules are available for multiple frequency bands and capable of fast frequency switching required to test the antenna. The DSP board contains additional peripherals that allows for more complex projects in the future. The block structure of the system is also very educational as each stage of transmission and reception can be tested and observed. The full system has been constructed and tested using simulated and real signals. A code was developed for communication between commercial modules and the DSP, bit error rate testing, data transmission, signal generation, and signal reception. A graphical user interface (GUI) was developed to help user with information display and system control. This thesis describes the software-defined-radio design in detail and shows test results at the end. / Master of Science

Modern public-key cryptography relies extensively on modular multiplication with long operands. We investigate the opportunities to optimize this operation in a heterogeneous multiprocessing platform such as TI OMAP3530. By migrating the long operand modular multiplication from a general-purpose ARM Cortex A8 to a specialized C64x+ VLIW DSP, we are able to exploit the XOR-Multiply instruction and the inherent parallelism of the DSP. The proposed multiplication utilizes Multi-Precision Binary Polynomial Multiplication with Unbalanced Exponent Modular Reduction. The resulting DSP implementation performs a GF(2^233) multiplication in less than 1.31us, which is over a seven times speed up when compared with the ARM implementation on the same chip. We present several strategies for different field sizes and field polynomials, and show that a 360MHz DSP easily outperforms the 500MHz ARM. / Master of Science