This master thesis report is a part of the thesis project conducted by Jakob Uhlin at Syntronic R R and D, Stockholm Sweden. The objective of this thesis is to develop a way to process the signal being sent on a CAN-bus and subsequently analyse its quality and its source in the network. A process of gathering appropriate theories and data has been done, parallel with the development of the analyzer module. The intelligence is implemented in an FPGA through the hardware description language VHDL. In this way, the algorithms can process the data in a real-time domain. The central findings and conclusions have been that is possible to analyze the signal quality of a CAN message properly on a FPGA.