This thesis focuses on the analysis theory, circuit design, simulations, and chip measurements of the transfer stage in the continuously error-trimming comparator-based switched-capacitor charge transfer stage in the cyclic redundant-sign-digit (RSD) algorithm. Capacitor mismatching remains an insurmountable factor for switched-capacitor circuit designers. To correct errors which result from the capacitor mismatching, a continuous error-trimming circuit is generalized from a typical CBSC circuit. The analysis theory of the error-trimming operation describes the effects of the error-trimming circuit in the CBSC circuit, as well as the guidelines for trimming. The error-trimming operation is able to tune the gain and virtual condition of the charge transfer stage for canceling the gain and offset errors. The circuit is designed, with the 0.35£gm 2-poly 4-metal TSMC process, in fully integral circuits. The circuit is simulated by a matlab simulator and an online Cadence Spectre simulator, to confirm how the operation works. Finally, chip measurements are recorded for verification and simulation comparisons.

The smart dust concept is a fairly recent phenomenon to engineering. It assumes monitoring of a real natural environment in which motes or smart dust machines swarm in collective and coordinate information among themselves and/or to a backend control platform. In analog mixed signal field work on such devices is gaining momentum such that it is conceived to be one of the emerging fields in technology, and work was only possible once the technology for fabrication touched the nanoscale regions. Smart dust network involves remote devices connected in a hive sensing burst type datum signals from the environment and relaying information amongst themselves in an energy efficient manner to coordinate an appropriate response to a detected stimulus. The project presumed a RF based communication strategy for coordination amongst the devices through a wireless medium. That is less susceptible to stringent requirements of LOS and a base band processing system that comprised of an environment sensor, an AFE module, an ADC, a DSP and a DAC. Essentially a 10 bit, 2 Mega Hertz MHz pipelined ADC implemented in a STM 65nm technology. The ADC benefits the smart dust device in allowing it to process data in an energy efficient way and also focusing on reduced complexity as itsdesign feature. While it differs in the other ADC of the system by operating at a higher frequency and assuming a different design philosophy assuming a coherent system sensitive to a clock. The thesis work assumes that various features ofenergy harvesting, regulation and power management present in the smart dustmote would enable the system to contain such a diverse ADC. The ADCs output digital datum would be compatible to the rest of the design modules consisting mainly of DSP sections. The ADC novelty is based on the fact that it removes the necessity of employing a high power consuming OpAmp whose design parameters become more complex as technology scales to the nanoscale era and further down. A systematic, bottom up, test driven approach to design is utilized and various behaviours of the system are captured in Cadence design environment with verilogto layout models and MATLAB and Simulink models.