This thesis will present the design, implementation, and testing of a high voltage Charge-Coupled Device (CCD) controller ASIC for the Large Synoptic Survey Telescope (LSST), which will be used to study dark energy and dark matter. The LSST observatory, which includes a 3.2-gigapixel camera, will cover the entire sky every three nights by taking continuous 15-second exposures. The CCD controller ASIC, or Sensor Control Chip (SCC), will provide five CCD driver channels that are capable of generating serial or parallel clock signals for the LSST’s imaging sensors during readout mode. The SCC will also provide three programmable bias voltages for the CCDs along with eight supplementary programmable voltages and currents for the CCD’s output drain terminals. Additionally, the controller ASIC includes eight control signals for a separate Analog Signal Processing Integrated Circuit (ASPIC) that is designed as the readout chip for LSST. The SCC is designed to operate down to 153 K. Fabricated in a commercially available 0.8-micron Bipolar-CMOS-DMOS Silicon-On-Insulator (BCD-SOI) process, the SCC has been verified to meet all design requirements.

This thesis will present the design, implementation, and testing of a high voltage Charge-Coupled Device (CCD) controller ASIC for the Large Synoptic Survey Telescope (LSST), which will be used to study dark energy and dark matter. The LSST observatory, which includes a 3.2-gigapixel camera, will cover the entire sky every three nights by taking continuous 15-second exposures. The CCD controller ASIC, or Sensor Control Chip (SCC), will provide five CCD driver channels that are capable of generating serial or parallel clock signals for the LSST’s imaging sensors during readout mode. The SCC will also provide three programmable bias voltages for the CCDs along with eight supplementary programmable voltages and currents for the CCD’s output drain terminals. Additionally, the controller ASIC includes eight control signals for a separate Analog Signal Processing Integrated Circuit (ASPIC) that is designed as the readout chip for LSST. The SCC is designed to operate down to 153 K. Fabricated in a commercially available 0.8-micron Bipolar-CMOS-DMOS Silicon-On-Insulator (BCD-SOI) process, the SCC has been verified to meet all design requirements.