High-speed, medium-resolution, analog-to-digital converters (ADCs) are important building blocks in a wide range of applications. High-speed, medium-resolution ADCs have been implemented by various ADC architectures such as a folding ADC, a subranging ADC, and a pipeline ADC. Among them, pipeline ADCs have proven to be efficient architectures for applications such as digital communication systems, data acquisition systems and video systems. Especially, power dissipation is a primary concern in applications requiring portability. Thus, the objective of this work is to design and build a low-voltage low-power medium-resolution (8-10bits) high-speed pipeline ADC in deep sub-micron CMOS technology. The non-idealities of the circuit realization are carefully investigated in order to identify the circuit requirements for a low power circuit design of a pipeline ADC. The resolution per stage plays an important role in determining overall power dissipation of a pipeline ADC. The pros and cons of both large and small number of bits per-stage are examined. A power optimization algorithm is developed to decide more accurately which approach is better for lower power dissipation. Both identical and non-identical number of bit per-stage approaches are considered and their differences are analyzed. A low-power, low-voltage 10-bit 100Msamples/s pipeline ADC was designed and implemented in a 0.18mm CMOS process. The power consumption was minimized with the right selection of the per-stage resolution based on the result of the power optimization algorithm and by the scaling down the sampling capacitor size in subsequent stages.

Ultra low power wireless sensors and sensor systems are of increasing interest in a variety of applications ranging from structural health monitoring to industrial process control. Electrochemical batteries have thus far remained the primary energy sources for such systems despite the finite associated lifetimes imposed due to limitations associated with energy density. However, certain applications (such as implantable biomedical electronic devices and tire pressure sensors) require the operation of sensors and sensor systems over significant periods of time, where battery usage may be impractical and add cost due to the requirement for periodic re-charging and/or replacement. In order to address this challenge and extend the operational lifetime of wireless sensors, there has been an emerging research interest on harvesting ambient vibration energy. Vibration energy harvesting is a technology that generates electrical energy from ambient kinetic energy. Despite numerous research publications in this field over the past decade, low power density and variable ambient conditions remain as the key limitations of vibration energy harvesting. In terms of the piezoelectric transducers, the open-circuit voltage is usually low, which limits its power while extracted by a full-bridge rectifier. In terms of the interface circuits, most reported circuits are limited by the power efficiency, suitability to real-world vibration conditions and system volume due to large off-chip components required. The research reported in this thesis is focused on increasing power output of piezoelectric transducers and power extraction efficiency of interface circuits. There are five main chapters describing two new design topologies of piezoelectric transducers and three novel active interface circuits implemented with CMOS technology. In order to improve the power output of a piezoelectric transducer, a series connection configuration scheme is proposed, which splits the electrode of a harvester into multiple equal regions connected in series to inherently increase the open-circuit voltage generated by the harvester. This topology passively increases the rectified power while using a full-bridge rectifier. While most of piezoelectric transducers are designed with piezoelectric layers fully covered by electrodes, this thesis proposes a new electrode design topology, which maximizes the raw AC output power of a piezoelectric harvester by finding an optimal electrode coverage. In order to extract power from a piezoelectric harvester, three active interface circuits are proposed in this thesis. The first one improves the conventional SSHI (synchronized switch harvesting on inductor) by employing a startup circuitry to enable the system to start operating under much lower vibration excitation levels. The second one dynamically configures the connection of the two regions of a piezoelectric transducer to increase the operational range and output power under a variety of excitation levels. The third one is a novel SSH architecture which employs capacitors instead of inductors to perform synchronous voltage flip. This new architecture is named as SSHC (synchronized switch harvesting on capacitors) to distinguish from SSHI rectifiers and indicate its inductorless architecture.