Abstract The main aim of this work was to design CMOS receiver channels for the integrated receiver chip of a pulsed time-of-flight (TOF) laser rangefinder. The chip includes both the receiver channel and the time-to-digital converter (TDC) in a single die, thus increasing the level of integration of the system, with the corresponding advantages of a cheaper price and lower power consumption, for example. Receiver channels with both linear and leading edge timing discriminator schemes were investigated. In general the receiver channel consists of a preamplifier, a postamplifier and a timing comparator. Since a large systematic timing error may occur due to high variation in the amplitude of the received echo, a leading edge timing discriminator scheme with time domain walk error compensation is proposed here, making use of the TDC already available in the chip to measure the slew rate of the pulse and using that information to evaluate the timing error. This compensation scheme benefits from the fact that compensation can be continued even though the signal is clipped in the amplitude domain, because the slew rate continues to increase even then. The receiver channel with leading edge detection and time domain walk error compensation achieved a compensated timing walk error of ±4.5 mm within a dynamic range of more than 1:10000. The standard deviation in single shot precision was less than 25 mm with an SNR of more than 20. The usability of the receiver channel in pulsed TOF laser rangefinders was verified by making actual time-of-flight measurements on a calibrated measurement track. The linearity of the receiver chip was better than ±5 mm in a measurement range from 3 m to 21 m, with the dynamic range of the receiver channel reaching more than 1:2000. An integrated CMOS laser diode pulser was also demonstrated to prove its functionality for generating ampere-scale peak current pulses through a low ohmic load and a laser diode. The CMOS pulser achieved a peak current pulse with the amplitude of ~1 A, an optical pulse width of ~2.5 ns and a rise time of ~1 ns with a 5 V power supply. / Tiivistelmä Työn ensisijaisena tavoitteena oli suunnitella CMOS-vastaanottimia valopulssin kulkuajan mittaukseen perustuvan lasertutkan integroituun vastaanotinpiiriin. Vastaanotinpiiri sisältää sekä vastaanotinkanavan että aika-digitaalimuuntimen yhdellä integroidulla sirulla. Tällöin systeemin integrointiastetta saadaan kasvatettua, mikä merkitsee esimerkiksi halvempaa hintaa ja pienempää tehon kulutusta. Työssä on tutkittu vastaanotinkanavia, jotka käyttävät joko lineaariseen ilmaisuun tai etureunailmaisuun perustuvaa ajoitusilmaisutekniikkaa. Yleisesti vastaanotinkanava sisältää esivahvistimen, jälkivahvistimen ja ajoituskomparaattorin. Vastaanotetun signaalin tason voimakas vaihtelu saattaa aiheuttaa suuren systemaattisen virheen etureunailmaisuun perustuvassa ajoitusilmaisussa. Tässä työssä on esitetty etureunailmaisua käyttävä ajoitusilmaisin, jossa syntyvää ajoitusvirhettä voidaan korjata mittaamalla pulssin nousunopeutta aika-digitaalimuuntimella, joka on integroitu samalle sirulle. Aikatasossa tapahtuvan virheenkorjauksen etuna on mahdollisuus jatkaa virheenkorjausta amplituditasossa tapahtuvan signaalin leikkautumisen jälkeenkin, koska signaalin nousunopeus kasvaa leikkaantumisesta huolimatta. Etureunailmaisua käyttävällä vastaanotinkanavalla, jossa ajoitusvirhettä korjattiin pulssin nousunopeutta mittaamalla, saavutettiin ±4,5 mm ajoitusvirhe 1:10000 dynaamisella alueella. Kertamittaustarkkuuden keskihajonta oli vähemmän kuin 25 mm, kun signaalikohinasuhde oli enemmän kuin 20. Vastaanotinkanavan käytettävyys osana lasertutkaa todettiin tekemällä tutkamittauksia kalibroidulla mittaradalla. Mittauksissa saavutettu lineaarisuus oli ±5 mm mittausalueen vaihdellessa 3 metristä 21 metriin ja signaalin dynamiikan ollessa enemmän kuin 1:2000. Lisäksi työssä esitellään integroitu CMOS-pulssitin, joka pystyy tuottamaan ampeeri-luokan virtapulsseja laserdiodiin. CMOS-pulssittimella voitiin tuottaa 5 V käyttöjännitteellä ~1 A virtapulsseja optisen pulssin leveyden ja nousuajan ollessa ~2,5 ns ja ~1 ns.

Abstract The goal of this work was to develop a CMOS receiver for a time-of-flight (TOF) laser rangefinder utilizing sub-ns pulses produced by a laser diode operating in gain switching mode (~ 1 nJ transmitter energy). This thesis also discusses the optical detector components and their usability with sub-ns optical pulses in laser rangefinding and the effect of the laser driver electronics on the shape of the sub-ns laser output, and eventually on the timing walk error of the laser rangefinder. The thesis presents the design of an integrated receiver channel IC intended for use in the pulsed TOF rangefinder. This is realized in a low-cost and consumer electronics-friendly CMOS technology (0.18 μm) and is based on a linear receiver and leading edge time discrimination. The measured walk error of the receiver is ~ 500 ps (4.5 cm in distance) within a 1:21,000 dynamic range. The measured jitter of the leading edge, affecting the single-shot precision of the radar, was ~ 12 ps (1.6 mm in distance) at an SNR > 200. In addition, a pulsed TOF rangefinder using the receiver IC developed here was designed and used for demonstrating the possibility of measuring tiny vibrations in a distant non-cooperative target. The radar was used successfully to observe 10 Hz vibrations in a non-cooperative target with an amplitude of 1.5 mm (sub-mm precision after averaging) at a distance of ~ 2 m. One important result was the demonstration of a difference in walk error behaviour between MOSFET and avalanche BJT-based laser pulse transmitters. The practicability of an integrated CMOS AP detector in sub-ns laser rangefinding was also studied. / Tiivistelmä Työn tavoitteena oli kehittää CMOS-vastaanotin valon kulkuaikamittaukseen perustuvaan laseretäisyysmittariin, joka hyödyntää ”gain-switching”-tekniikalla toimivan laserdiodin (~ 1 nJ energia) tuottamia alle nanosekuntiluokan laserpulsseja. Väitöskirja tutkii myös valovastaanotinkomponenttien käyttökelpoisuutta alle nanosekuntiluokan laserpulsseja hyödyntävässä laseretäisyysmittauksessa. Työssä tutkitaan myös laserdiodilähettimen elektroniikan vaikutusta alle nanosekuntiluokan laserpulssien muotoon ja lopulta niiden vaikutusta systemaattiseen ajoitusvirheeseen laseretäisyysmittauksessa. Väitöskirja esittelee suunnitellun valopulssin kulkuaikamittaukseen perustuvaan laseretäisyysmittariin soveltuvan integroidun vastaanotinkanavan IC-piirin. Se on toteutettu halvalla, kulutuselektroniikkaan soveltuvalla CMOS tekniikalla (0,18 μm) ja se perustuu lineaariseen vastaanottimeen ja nousevan reunan ilmaisuun. Vastaanottimen mitattu systemaattinen ajoitusvirhe on ~ 500 ps (4,5 cm matkassa) 1:21 000 signaalivoimakkuuden vaihtelualueella. Vastaanottimesta mitattu laseretäisyysmittarin kertamittaustarkkuuteen vaikuttava nousevan reunan satunnainen ajoitusepävarmuus oli ~ 12 ps (1.6 mm matkassa) signaalikohinasuhteella > 200. Lisäksi tässä työssä toteutettiin kehitettyä vastaanotin-IC piiriä hyödyntävä valopulssin kulkuaikamittaukseen perustuva etäisyysmittari, jolla kyettiin havainnollistamaan mahdollisuutta mitata pientä tärinää kaukaisessa passiivisessa kohteessa. Tutkalla onnistuttiin havainnoimaan 1,5 mm vaihteluväliltään olevaa 10 Hz tärinä ~ 2 m etäisyydellä olevasta kohteesta. Väitöskirjan yksi tärkeä tulos oli havainnollistaa systemaattisessa ajoitusvirheessä havaittava ero MOSFET-transistoriin ja vyöry-BJT-transistoriin perustuvan laserpulssilähettimen välillä. Integroidun CMOS AP vastaanotinkomponentin käyttökelpoisuus alle nanosekuntiluokan laseretäisyysmittauksessa tutkittiin myös.

This dissertation focuses on design and implementation of a highly linear and low flicker-noise receiver front-end based on the direct conversion architecture for multiband applications in a CMOS technology. The dissertation consists of two parts: One, implementation of a highly linear RF receiver front-end and, two, implementation of a low flicker-noise RF receiver front-end based for direct conversion architecture. For multiband applications, key active components, highly linear LNAs and mixers, in the RF front-end receiver have been implemented in a 0.18um CMOS process. Theoretical approaches are analyzed from the perspective of implementation issues for highly linear receiver system and are also compared with measured results. Highly linear LNAs and mixers have been analyzed in terms of noise, linearity and power consumption, etc. For a low flicker-noise receiver front-end based on direct conversion architecture, the design of differential LNA and various low flicker-noise mixers are investigated in a standard 0.18um CMOS process. A differential LNA which shows high linearity was fabricated with a low flicker-noise mixer. Three low flicker-noise mixers were designed, measured and compared to the-state-of-the-arts published by other research institutes and companies.

LOW power operation for wireless radio receivers has been gaining importance lately on account of the recent spurt of growth in the usage of ubiquitous embedded mobile devices. These devices are becoming relevant in all domains of human influence. In most cases battery life for these devices continue to be an us-age bottleneck as energy storage techniques have not kept pace with the growing demand of such mobile computing devices. Many applications of these radios have limitations on recharge cycle, i.e. the radio needs to last out of a battery for long duration. This will specially be true for sensor network applications and for im-plantable medical devices. The search for low power wireless receivers has become quite advanced with a plethora of techniques, ranging from circuit to architecture to system level approaches being formulated as part of standard design procedures. However the next level of optimization towards “Smart” receiver systems has been gaining credence and may prove to be the next challenge in receiver design and de-velopment. We aim to proceed further on this journey by proposing Power Scalable Wireless Receivers (PSRX) which have the capability to respond to instantaneous performance requirements to lower power even further. Traditionally low power receivers were designed for worst-case input conditions, namely low signal and high interference, leading to large dynamic range of operation which directly im-pacts the power consumption. We propose to take into account the variation in performance required out of the receiver, under varying Signal and Interference conditions, to trade-off power. We have analyzed, designed and implemented a Power Scalable Receiver tar-geted towards low data-rate receivers which can work for Zigbee or Bluetooth Low Energy (BLE) type standards. Each block of such a receiver system was evaluated for performance-power trade-offs leading to identification of tuning/control knobs at the circuit architecture level of the receiver blocks. Then we developed an usage algorithm for finding power optimal operational settings for the tuning knobs, while guaranteeing receiver reception performance in terms of Bit-Error-Rate (BER). We have proposed and demonstrated a novel signal measurement system to gen-erate digitized estimates of signal and interference strength in the received signal, called Received Signal Quality Indicator (RSQI). We achieve a RSQI average energy consumption of 8.1nJ with a peak energy consumption of 9.4nJ which is quite low compared to the packet reception energy consumption for low power receivers, and will be substantially lower than the energy savings which will be achieved from a power scalable receiver employing a RSQI. The full PSRX system was fabricated in UMC 130nm RF-CMOS process to test out our concepts and to formally quantify the power savings achieved by following the design methodology. The test chip occupied an area of 2.7mm2 with a peak power consumption of 5.5mW for the receiver chain and 18mW for the complete PSRX. We were able to meet the receiver performance requirements for Zigbee standard and achieved about 5X power savings for the range of input condition variations.