In the 2010, targets of National Science and Technology Program - Energy¡¥s project plan had mentioned about the development of power line communication (PLC). This shows the importance of PLC. The data transmission occur burst errors easily by the noise interference from the environment. In order to reduce the error rate, we design a modulation/demodulation chip with error correctable and high error detected ability for power line communication in this thesis. The proposed design consists of Cyclic Redundancy Check (CRC), Pulse Width Modulation (PWM), Frequency Shift Keying (FSK), Forward Error Correction (i.e. binary BCH code), and interleaving techniques. The CRC can detect the errors occurred in the digital communication. The probability of finding error is 99.997%. The BCH code is capable of correcting any combination of 3 or fewer errors in block. The function of PWM is to generate the digital pulses that exhibit the changeable pulse width according to the swing of the input voltage. In the telecommunication, FSK is a frequency modulation scheme such that the digital information can be transmitted through the discrete frequency changes of the carrier. Interleaving can make burst errors look like random errors. The design is implemented TSMC 0.18£gm process. The fabricated chip area is 1.16 millimeter square with 3.3V/1.8V supply voltages. The measured data shows that the proposed design is fully functional and consumes 55.5 £gW.