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Power reduction techniques for memory elements /Katrue, Srikanth. January 2007 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 2007. / Typescript. Includes bibliographical references (leaves 58-60).
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Power reduction of MPEG video decoding for mobile multimedia systems /Lewis, James M. January 1900 (has links)
Thesis (M.S.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaves 33-34). Also available on the World Wide Web.
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283 |
On the use and performance of communication primitives in software controlled cache-coherent cluster architectures /Qin, Xiaohan, January 1997 (has links)
Thesis (Ph. D.)--University of Washington, 1997. / Vita. Includes bibliographical references (leaves [117]-125).
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Cache design and timing analysis for preemptive multi-tasking real-time uniprocessor systemsTan, Yudong. January 2005 (has links) (PDF)
Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. / Schimmel, David, Committee Member ; Meliopoulos, A. P. Sakis, Committee Member ; Mooney, Vincent, Committee Chair ; Prvulovic, Milos, Committee Member ; Yalamanchili, Sudhakar, Committee Member. Includes bibliographical references.
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285 |
Design and implementation of configuration modules in a programmable hardware-assisted cache emulator (PHA$E) /Chalainanont, Nirut. January 1900 (has links)
Thesis (M.S.)--Oregon State University, 2005. / Printout. Includes bibliographical references (leaves 38-40). Also available on the World Wide Web.
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286 |
A study for reducing conflict misses in data cacheAmmari, Rami J. January 2004 (has links)
Thesis (M.S.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.
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287 |
Cache architectures to improve IP lookupsRavinder, Sunil. January 2009 (has links)
Thesis (M.Sc.)--University of Alberta, 2009. / Title from PDF file main screen (viewed on Mar. 18, 2010). A thesis submitted to the Faculty of Graduate Studies and Research in partial fulfillment of the requirements for the degree of Master of Science, Department of Computing Science, University of Alberta. Includes bibliographical references.
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Kommunikationsmechanismen für paralleles, adaptives Level-of-Detail in VR-SimulationenSchwarze, Tino, January 2003 (has links)
Chemnitz, Techn. Univ., Diplomarb., 2003.
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Adaptive Verfahren höherer Ordnung auf cache-optimalen Datenstrukturen für dreidimensionale ProblemeKrahnke, Andreas. January 2005 (has links) (PDF)
München, Techn. Univ., Diss., 2005.
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Single-level dynamic register caching architecture for high-performance superscalar processors /Liebert, John A. January 1900 (has links)
Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 30-32). Also available on the World Wide Web.
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