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Low-energy instruction cache architecture /Ali, Kashif. January 2006 (has links)
Thesis (M.Sc.)--York University, 2006. Graduate Programme in Computer Science. / Typescript. Includes bibliographical references (leaves 96-107). Also available on the Internet. MODE OF ACCESS via web browser by entering the following URL: http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&res_dat=xri:pqdiss&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft_dat=xri:pqdiss:MR19752
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Cache-oblivious query processing /He, Bingsheng. January 2008 (has links)
Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2008. / Includes bibliographical references (leaves 89-100). Also available in electronic version.
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Data prefetching for high-performance processors /Chen, Tien-Fu, January 1993 (has links)
Thesis (Ph. D.)--University of Washington, 1993. / Vita. Includes bibliographical references (leaves [121]-129).
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Data caching in wireless mobile networks /Xu, Ji. January 2004 (has links)
Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004. / Includes bibliographical references (leaves 57-60). Also available in electronic version. Access restricted to campus users.
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Array restructuring for cache locality /Leung, Shun-Tak Albert. January 1996 (has links)
Thesis (Ph. D.)--University of Washington, 1996. / Vita. Includes bibliographical references (p. [177]-186).
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Latency reduction techniques for remote memory access in ANEMONELewandowski, Mark. Gopalan, Kartik. January 2006 (has links)
Thesis (M.S.)--Florida State University, 2006. / Advisor: Kartik Gopalan, Florida State University, College of Arts and Sciences, Dept. of Computer Science. Title and description from dissertation home page (viewed June 6, 2006). Document formatted into pages; contains ix, 43 pages. Includes bibliographical references.
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Scalable primary cache memory architecturesAgarwal, Vikas. John, Lizy Kurian, Keckler, Stephen W., January 2004 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2004. / Supervisors: Lizy K. John and Stephen W. Keckler. Vita. Includes bibliographical references.
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Multipurpose short-term memory structures.January 1995 (has links)
by Yung, Chan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 107-110). / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Cache --- p.1 / Chapter 1.1.1 --- Introduction --- p.1 / Chapter 1.1.2 --- Data Prefetching --- p.2 / Chapter 1.2 --- Register --- p.2 / Chapter 1.3 --- Problems and Challenges --- p.3 / Chapter 1.3.1 --- Overhead of registers --- p.3 / Chapter 1.3.2 --- EReg --- p.5 / Chapter 1.4 --- Organization of the Thesis --- p.6 / Chapter 2 --- Previous Studies --- p.8 / Chapter 2.1 --- Introduction --- p.8 / Chapter 2.2 --- Data aliasing --- p.9 / Chapter 2.3 --- Data prefetching --- p.12 / Chapter 2.3.1 --- Introduction --- p.12 / Chapter 2.3.2 --- Hardware Prefetching --- p.12 / Chapter 2.3.3 --- Prefetching with Software Support --- p.13 / Chapter 2.3.4 --- Reducing Cache Pollution --- p.14 / Chapter 3 --- BASIC and ADM Models --- p.15 / Chapter 3.1 --- Introduction of Basic Model --- p.15 / Chapter 3.2 --- Architectural and Operational Detail of Basic Model --- p.18 / Chapter 3.3 --- Discussion --- p.19 / Chapter 3.3.1 --- Implicit Storing --- p.19 / Chapter 3.3.2 --- Associative Logic --- p.22 / Chapter 3.4 --- Example for Basic Model --- p.22 / Chapter 3.5 --- Simulation Results --- p.23 / Chapter 3.6 --- Temporary Storage Problem in Basic Model --- p.29 / Chapter 3.6.1 --- Introduction --- p.29 / Chapter 3.6.2 --- Discussion on the Solutions --- p.31 / Chapter 3.7 --- Introduction of ADM Model --- p.35 / Chapter 3.8 --- Architectural and Operational Detail of ADM Model --- p.37 / Chapter 3.9 --- Discussion --- p.39 / Chapter 3.9.1 --- File Partition --- p.39 / Chapter 3.9.2 --- STORE Instruction --- p.39 / Chapter 3.10 --- Example for ADM Model --- p.40 / Chapter 3.11 --- Simulation Results --- p.40 / Chapter 3.12 --- Temporary storage Problem of ADM Model --- p.46 / Chapter 3.12.1 --- Introduction --- p.46 / Chapter 3.12.2 --- Discussion on the Solutions --- p.46 / Chapter 4 --- ADS Model and ADSM Model --- p.49 / Chapter 4.1 --- Introduction of ADS Model --- p.49 / Chapter 4.2 --- Architectural and Operational Detail of ADS Model --- p.50 / Chapter 4.3 --- Discussion --- p.52 / Chapter 4.3.1 --- Prefetching Priority --- p.52 / Chapter 4.3.2 --- Data Prefetching --- p.53 / Chapter 4.3.3 --- EReg File Splitting --- p.53 / Chapter 4.3.4 --- Compiling Procedure --- p.53 / Chapter 4.4 --- Example for ADS Model --- p.54 / Chapter 4.5 --- Simulation Results --- p.55 / Chapter 4.6 --- Discussion on the Architectural and Operational Variations for ADS Model --- p.62 / Chapter 4.6.1 --- Temporary storage Problem --- p.62 / Chapter 4.6.2 --- Operational variation for Data Prefetching --- p.63 / Chapter 4.7 --- Introduction of ADSM Model --- p.64 / Chapter 4.8 --- Architectural and Operational Detail of ADSM Model --- p.65 / Chapter 4.9 --- Discussion --- p.67 / Chapter 4.10 --- Example for ADSM Model --- p.67 / Chapter 4.11 --- Simulation Results --- p.68 / Chapter 4.12 --- Discussion on the Architectural and Operational Variations for ADSM Model --- p.71 / Chapter 4.12.1 --- Temporary storage Problem --- p.71 / Chapter 4.12.2 --- Operational variation for Data Prefetching --- p.73 / Chapter 5 --- IADSM Model and IADSMC&IDLC Model --- p.75 / Chapter 5.1 --- Introduction of IADSM Model --- p.75 / Chapter 5.2 --- Architectural and Operational Detail of IADSM Model --- p.76 / Chapter 5.3 --- Discussion --- p.79 / Chapter 5.3.1 --- Implicit Loading --- p.79 / Chapter 5.3.2 --- Compiling Procedure --- p.81 / Chapter 5.4 --- Example for IADSM Model --- p.81 / Chapter 5.5 --- Simulation Results --- p.84 / Chapter 5.6 --- Temporary Storage Problem of IADSM Model --- p.87 / Chapter 5.7 --- Introduction of IADSMC&IDLC Model..........: --- p.88 / Chapter 5.8 --- Architectural and Operational Detail of IADSMC & IDLC Model --- p.89 / Chapter 5.9 --- Discussion --- p.90 / Chapter 5.9.1 --- Additional Operations --- p.90 / Chapter 5.9.2 --- Compiling Procedure --- p.93 / Chapter 5.10 --- Example for IADSMC&IDLC Model --- p.93 / Chapter 5.11 --- Simulation Results --- p.94 / Chapter 5.12 --- Temporary Storage Problem of IADSMC&IDLC Model --- p.96 / Chapter 6 --- Compiler and Memory System Support for EReg --- p.99 / Chapter 6.1 --- Impact on Compiler --- p.99 / Chapter 6.1.1 --- Register Usage --- p.99 / Chapter 6.1.2 --- Effect of Unrolling --- p.100 / Chapter 6.1.3 --- Code Scheduling Algorithm --- p.101 / Chapter 6.2 --- Impact on Memory System --- p.102 / Chapter 6.2.1 --- Memory Bottleneck --- p.102 / Chapter 6.2.2 --- Size of EReg Files --- p.103 / Chapter 7 --- Conclusions --- p.104 / Chapter 7.1 --- Summary --- p.104 / Chapter 7.2 --- Future Research --- p.105 / Bibliography --- p.107 / Chapter A --- Source code of the Kernels --- p.111 / Chapter B --- Program Analysis --- p.126 / Chapter B.1 --- Program analysed by Basic Model --- p.126 / Chapter B.2 --- Program analysed by ADM Model --- p.133 / Chapter B.3 --- Program analysed by ADS Model --- p.140 / Chapter B.4 --- Program analysed by ADSM Model --- p.148 / Chapter B.5 --- Program analysed by IADSM Model --- p.156 / Chapter B.6 --- Program analysed by IADSMC&IDLC Model --- p.163 / Chapter C --- Cache Simulation on Prefetching of ADS model --- p.174
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Real-time cache design.January 1996 (has links)
by Hon-Kai, Cheung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. / Includes bibliographical references (leaves 102-105). / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview --- p.1 / Chapter 1.2 --- Scheduling In Real-time Systems --- p.4 / Chapter 1.3 --- Cache Memories --- p.5 / Chapter 1.4 --- Outline Of The Dissertation --- p.8 / Chapter 2 --- Related Work --- p.9 / Chapter 2.1 --- Introduction --- p.9 / Chapter 2.2 --- Predictable Cache Designs --- p.9 / Chapter 2.2.1 --- Locking Cache Lines Design --- p.9 / Chapter 2.2.2 --- Partially Dynamic And Static Cache Partition Allocation Design --- p.10 / Chapter 2.2.3 --- SMART (Strategic Memory Allocation for Real Time) Cache Design --- p.10 / Chapter 2.3 --- Prefetching --- p.11 / Chapter 2.3.1 --- Introduction --- p.11 / Chapter 2.3.2 --- Hardware Support Prefetching --- p.12 / Chapter 2.3.3 --- Software Assisted Prefetching --- p.12 / Chapter 2.3.4 --- Partial Cache Hit --- p.13 / Chapter 2.3.5 --- Cache Pollution Problems --- p.13 / Chapter 2.4 --- Cache Line Replacement Policies --- p.13 / Chapter 2.5 --- Main Memory Update Policies --- p.14 / Chapter 2.6 --- Summaries --- p.15 / Chapter 3 --- Problems And Motivations --- p.16 / Chapter 3.1 --- Introduction --- p.16 / Chapter 3.2 --- Problems --- p.16 / Chapter 3.2.1 --- Modern Cache Architecture Is Inappropriate For Real-time Systems --- p.16 / Chapter 3.2.2 --- Intertask Interference: The Effects Of Preemption --- p.17 / Chapter 3.2.3 --- Intratask Interference: Cache Line Collision --- p.20 / Chapter 3.3 --- Motivations --- p.21 / Chapter 3.3.1 --- Improvement Of The Cache Performance In Real-time Systems --- p.21 / Chapter 3.3.2 --- Hiding of Preemption Effects --- p.22 / Chapter 3.4 --- Conclusions --- p.25 / Chapter 4 --- Proposed Real-Time Cache Design --- p.26 / Chapter 4.1 --- Introduction --- p.26 / Chapter 4.2 --- Concepts Definition --- p.26 / Chapter 4.2.1 --- Tasks Definition --- p.26 / Chapter 4.2.2 --- Cache Performance Values --- p.27 / Chapter 4.3 --- Issues Related To Proposed Real-Time Cache Design --- p.28 / Chapter 4.3.1 --- A Task Serving Policy --- p.30 / Chapter 4.3.2 --- Number Of Private And Shared Cache Partitions --- p.31 / Chapter 4.3.3 --- Controlling The Cache Partitions: Cache Partition Table And Pro- cess Info Table --- p.32 / Chapter 4.3.4 --- Re-organization Of Task Owns Cache Partition(s) --- p.34 / Chapter 4.3.5 --- Handling The Bus Bandwidth: Memory Requests Queue ( MRQ ) --- p.35 / Chapter 4.3.6 --- How To Address The Cache Models --- p.37 / Chapter 4.3.7 --- Data Coherence Problems For Partitioned Cache Model And Non- partitioned Cache Model --- p.39 / Chapter 4.4 --- Mechanism For Proposed Real-Time Cache Design --- p.43 / Chapter 4.4.1 --- Basic Operation Of Proposed Real-Time Cache Design --- p.43 / Chapter 4.4.2 --- Assumptions And Rules --- p.43 / Chapter 4.4.3 --- First Round Dynamic Cache Partition Re-allocation --- p.44 / Chapter 4.4.4 --- Later Round Dynamic Cache Partition Re-allocation --- p.45 / Chapter 5 --- Simulation Environments --- p.56 / Chapter 5.1 --- Proposed Architectural Model --- p.56 / Chapter 5.2 --- Working Environment For Proposed Real-time Cache Models --- p.57 / Chapter 5.2.1 --- Cost Model --- p.57 / Chapter 5.2.2 --- System Model --- p.64 / Chapter 5.2.3 --- Fair Comparsion Between The Unified Cache And The Separate Caches --- p.64 / Chapter 5.2.4 --- Operations Within The Preemption --- p.65 / Chapter 5.3 --- Benchmark Programs --- p.65 / Chapter 5.3.1 --- The NASA7 Benchmark --- p.66 / Chapter 5.3.2 --- The SU2COR Benchmark --- p.66 / Chapter 5.3.3 --- The TOMCATV Benchmark --- p.66 / Chapter 5.3.4 --- The WAVE5 Benchmark --- p.67 / Chapter 5.3.5 --- The COMPRESS Benchmark --- p.67 / Chapter 5.3.6 --- The ESPRESSO Benchmark --- p.68 / Chapter 5.4 --- Simulations Parameters --- p.68 / Chapter 6 --- Analysis Of Simulations --- p.71 / Chapter 6.1 --- Introduction --- p.71 / Chapter 6.2 --- Trace Files Statistics --- p.71 / Chapter 6.3 --- Interpretation Of Partial Cache Hit --- p.72 / Chapter 6.4 --- The Effects Of Cache Size --- p.72 / Chapter 6.4.1 --- "Performances Of Model 1, Model 2, Model 3 And Model 4" --- p.72 / Chapter 6.5 --- The Effects Of Cache Partition Size --- p.76 / Chapter 6.5.1 --- Performance Of Model 3 --- p.79 / Chapter 6.5.2 --- Performance Of Model 1 --- p.79 / Chapter 6.6 --- The Effects Of Line Size --- p.80 / Chapter 6.6.1 --- "Performance Of Model 1, Model 2, Model 3 And Model 4" --- p.80 / Chapter 6.7 --- The Effects Of Set Associativity --- p.83 / Chapter 6.7.1 --- "Performance Of Model 1, Model 2, Model 3 And Model 4" --- p.83 / Chapter 6.8 --- The Effects Of The Best-expected Cache Performance --- p.84 / Chapter 6.8.1 --- Performance of Model 1 --- p.87 / Chapter 6.8.2 --- Performance of Model 3 --- p.88 / Chapter 6.9 --- The Effects Of The Standard-expected Cache Performance --- p.89 / Chapter 6.9.1 --- Performance Of Model 1 --- p.89 / Chapter 6.9.2 --- Performance Of Model 3 --- p.91 / Chapter 6.10 --- The Effects Of Cycle Execution Time/Cycle Deadline Period --- p.92 / Chapter 6.10.1 --- "Performances Of Model 1, Model 2, Model 3 And Model 4" --- p.92 / Chapter 7 --- Conclusions And Future Work --- p.95 / Chapter 7.1 --- Conclusions --- p.95 / Chapter 7.1.1 --- Unified Cache Model Is More Suitable In Real-time Systems --- p.99 / Chapter 7.1.2 --- Comments On Aperiodic Tasks --- p.100 / Chapter 7.2 --- Future Work --- p.100
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An energy efficient cache design using spin torque transfer (STT) RAMRasquinha, Mitchelle 23 August 2011 (has links)
The advent of many core architectures has coincided with the energy and power
limited design of modern processors. Projections for main memory clearly show
widening of the processor-memory gap. Cache capacity increased to help reduce
this gap will lead to increased energy and area usage and due to small growth in
die size, impede performance scaling that has accompanied Moore's Law to date.
Among the dominant sources of energy consumption is the on-chip memory hierar-
chy, specically the L2 cache and the Last Level Cache (LLC). This work explores
the use of a novel non-volatile memory technology - Spin Torque Transfer RAM
(STT RAM)" for the design of the L2/LLC caches. While STTRAM is a promising
memory technology, it has some limitations, particularly in terms of write energy and
write latencies. The main objectives of this thesis is to use a novel cell design for a
non-volatile 1T1MTJ cell and demonstrate its use at the L2 and LLC cache levels
with architectural optimizations to maximize energy reduction. The proposed cache
hierarchy dissipates significantly lesser energy (both leakage and dynamic) and uses
less area in comparison to a conventional SRAM based cache designs.
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