Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 143-150), Copy 2 (p. 135-142). Available also in a digital version from Dissertation Abstracts.

Thesis (M.S.)--The University of North Carolina at Greensboro, 2010. / Directed by Jing Deng; submitted to the Dept. of Computer Science. Title from PDF t.p. (viewed Jul. 12, 2010). Includes bibliographical references (p. 21-22).

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--Washington State University, August 2007. / Includes bibliographical references (p. 103-105).

Universiẗat, Diss., 1998--Saarbrücken.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 312-319). Available also in a digital version from Dissertation Abstracts.

Στα πλαίσια της παρούσας διπλωματικής εργασίας υλοποιήθηκε ένας εξομοιωτής κρυφών μνημών και ένας επεξεργαστής αρχιτεκτονικής τύπου MIPS σε γλώσσα προγραμματισμού Java. Με την χρήση του εξομοιωτή και ενός αλγορίθμου πολλαπλασιασμού πίνακα επί πίνακα γραμμένο σε συμβολική γλώσσα assembly αξιολογήθηκαν τα χαρακτηριστικά των κρυφών μνημών όπως συσχετιστικότητα, μέγεθος μπλοκ, μέγεθος μνήμης και ιεραρχία μνήμης. Ως αποτέλεσμα κατασκευάστηκε ένα εργαλείο αξιολόγησης τόσο της αρχιτεκτονικής του υλικού για έναν αλγόριθμο όσο και της αποδοτικότητας ενός αλγορίθμου που εισάγεται στο πρόγραμμα για μια αρχιτεκτονική. / In the context of the current thesis a cache memory simulator was implemented with a MIPS architecture processor in Java programming language. Using the simulator and a matrix by matrix multiplication algorithm written in assembly language supported by the simulator various features of the cache memories were evaluated such as associativity, block size, memory size and memory hierarchy. As a result an evaluation tool was built, capable of evaluating not only a memory hierarchy architecture but also the efficiency of an algorithm used on a specific architecture.

AN ABSTRACT OF THE THESIS OF Jeffery R. Brewer, for the Master degree in Electrical Computer Engineer, presented on May 22, 2009 at Southern Illinois University Carbondale. TITLE: Reconfigurable Cache Memory MAJOR PROFESSOR: Dr. Nazeih Botros As chip designers continue to push the performance of microprocessors to higher levels the energy demand grows. The increase need for integrated chips that provide energy savings without degrading performance is paramount. The cache memory is typically over fifty percent of the size of today's microprocessor chip, and consumes a significant percentage of the total power. Therefore, by designing a reconfigurable cache that's able to dynamically adjust to a smaller cache size without encountering a significant degrade in performance, we are able to realize power conservation. Tournament caching is a reconfigurable method that tracks the current performance of the cache and compares it to possible smaller or larger cache size [1] . The results in this thesis shows that reconfigurable cache memory implemented with a configuration mechanism like Tournament caching would take advantage of associativity and cache size while providing energy conservation. i