Finite impulse response (FIR) digital filters are frequently used in many digital signal processing and communication applications, such as IS-95 CDMA, Digital Mobile Phone Systems (D-AMPS), etc. FIR filter achieves the frequency response of system requirement using a series of multiplications and additions. Previous papers on FIR hardware implementations usually focus on reducing area and delay of the multiple constant multiplications (MCM) through common sub-expression elimination (CSE) in the transpose FIR filter structure. In this thesis, we first perform optimization for the quantization of FIR filter coefficients that satisfy the target frequency response. Then suitable encoding methods are adopted to reduce the height of the partial products of the MCM in the direct FIR filter structure. Finally, by jointly considering the errors in the truncated multiplications and additions, we can design the hardware-efficient FIR filter that meets the bit accuracy requirement. Experimental results show that although CSE in the transpose FIR structure can reduce more area in MCM, the direct form takes smaller area in registers. Compared with previous approaches, the proposed FIR implementations with direct form has the minimum area cost.