abstract: Micro Electro Mechanical Systems (MEMS) is one of the fastest growing field in silicon industry. Low cost production is key for any company to improve their market share. MEMS testing is challenging since input to test a MEMS device require physical stimulus like acceleration, pressure etc. Also, MEMS device vary with process and requires calibration to make them reliable. This increases test cost and testing time. This challenge can be overcome by combining electrical stimulus based testing along with statistical analysis on MEMS response for electrical stimulus and also limited physical stimulus response data. This thesis proposes electrical stimulus based built in self test(BIST) which can be used to get MEMS data and later this data can be used for statistical analysis. A capacitive MEMS accelerometer is considered to test this BIST approach. This BIST circuit overhead is less and utilizes most of the standard readout circuit. This thesis discusses accelerometer response for electrical stimulus and BIST architecture. As a part of this BIST circuit, a second order sigma delta modulator has been designed. This modulator has a sampling frequency of 1MHz and bandwidth of 6KHz. SNDR of 60dB is achieved with 1Vpp differential input signal and 3.3V supply / Dissertation/Thesis / M.S. Electrical Engineering 2013

abstract: The applications which use MEMS accelerometer have been on rise and many new fields which are using the MEMS devices have been on rise. The industry is trying to reduce the cost of production of these MEMS devices. These devices are manufactured using micromachining and the interface circuitry is manufactured using CMOS and the final product is integrated on to a single chip. Amount spent on testing of the MEMS devices make up a considerable share of the total final cost of the device. In order to save the cost and time spent on testing, researchers have been trying to develop different methodologies. At present, MEMS devices are tested using mechanical stimuli to measure the device parameters and for calibration the device. This testing is necessary since the MEMS process is not a very well controlled process unlike CMOS. This is done using an ATE and the cost of using ATE (automatic testing equipment) contribute to 30-40% of the devices final cost. This thesis proposes an architecture which can use an Electrical Signal to stimulate the MEMS device and use the data from the MEMS response in approximating the calibration coefficients efficiently. As a proof of concept, we have designed a BIST (Built-in self-test) circuit for MEMS accelerometer. The BIST has an electrical stimulus generator, Capacitance-to-voltage converter, ∑ ∆ ADC. This thesis explains in detail the design of the Electrical stimulus generator. We have also designed a technique to correlate the parameters obtained from electrical stimuli to those obtained by mechanical stimuli. This method is cost effective since the additional circuitry needed to implement BIST is less since the technique utilizes most of the existing standard readout circuitry already present. / Dissertation/Thesis / M.S. Electrical Engineering 2014

This thesis presents a detailed SIMULINK model for a conventional capacitive &amp / #931 / -&amp / #916 / accelerometer system consisting of a MEMS accelerometer, closed-loop readout electronics, and signal processing units (e.g. decimation filters). By using this model, it is possible to estimate the performance of the full accelerometer system including individual noise components, operation range, open loop sensitivity, scale factor, etc. The developed model has been verified through test results using a capacitive MEMS accelerometer, full-custom designed readout electronics, and signal processing unit implemented on a FPGA. Conventional accelerometer system with force-feedback is used in this thesis. The sensor is a typical capacitive lateral accelerometer. The readout electronics form a 2nd order electromechanical &amp / #931 / -&amp / #916 / modulator together with the accelerometer, and provide a single-bit PDM output, which is decimated and filtered with a signal processing unit, software implemented on a FPGA. The whole system is modeled in MATLAB-SIMULINK since it has both mechanical and electrical parts. To verify the model, two accelerometer systems are implemented. Each accelerometer system is composed of a MEMS accelerometer, readout circuit, and decimation filters. These two different designs are implemented and simulation and test results are compared in terms of output noise, operational range, open loop sensitivity, and scale factor. The first design operates at 500 kHz sampling rate and has 0.48 V/g open-loop sensitivity, 58.7 &micro / g/&amp / #8730 / Hz resolution, &plusmn / 12g operation range, and 0.97*10-6 g/(output units) scale factor, where these numbers are in close agreement with the estimated results found with simulations. Similarly, the second design operates at 500 kHz sampling rate and has 0.45 V/g open-loop sensitivity, 373.3 &micro / g/&amp / #8730 / Hz resolution, &plusmn / 31g operation range, and 2.933*10-6 g/(output units) scale factor, where these numbers are also close to the estimated results found with simulations. Within this thesis study, an accelerometer sensing element design algorithm is also proposed which is based on the theoretical background obtained in accelerometer system SIMULINK model. This algorithm takes the requirements of the desired accelerometer as input and outputs the dimensions of the minimum noise accelerometer satisfying these requirements. The algorithm is extended to design three different accelerometer structures. An accelerometer sensing element is designed using the proposed design algorithm and tested in order to see performance matching of the algorithm. The designed accelerometer has &plusmn / 33.02g operational range and 155&micro / g/&amp / #8730 / Hz noise where these numbers matches with the values found by the algorithm