Thesis (M.S.)--University of Missouri-Columbia, 2006. / The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on April 17, 2009) Includes bibliographical references.

Approved for public release; distribution is unlimited / The main focus in the design of the next generation combatant, DD(X), is the US Navy's proposed Integrated Power System (IPS) which includes an all-electric propulsion drive system. The reduction of current waveform harmonics is critical in combatant propulsion systems such as the IPS. One method of reducing the current harmonics is to utilize a multilevel converter topology. The multi-level converter, as compared to a standard converter, features low dv/dt losses and low switching losses. This thesis examines the design, construction and testing of two multi-level converters operated in tandem, called a Cascaded Multi-Level Converter (CMLC). A digital logic switching circuit is designed and constructed to control the CMLC during the operational testing phase. The CMLC is demonstrated in a three-phase high-voltage configuration with 178.5 V zero-to-peak voltage, 2.10 A zero-to-peak current achieved using an R-L load. / Lieutenant Commander, United States Navy

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2003. / Thesis advisor(s): Robert W. Ashton, John G. Ciezki, Douglas J. Fouts. Includes bibliographical references (p. 125-126). Also available online.

No description available.

Oversampling analog-to-digital and digital-to-analog converters are gaining more popularity in many signal processing applications. Delta-sigma modulators are used in practical applications of oversampling systems because of their apparent practical advantage over other oversampling converters in terms of insensitivity to the inevitable imperfection of the analog circuitry. In Δ∑ modulators, analog integrators are always very important components and are usually modeled as ideal in real applications. However, theoretical analysis shows that the integrator nonideality due to capacitor mismatching and finite op-amp gain cause large signal-to-noise ratio degradation. The primary disadvantages of the dual-quantization and cascade modulators are that they rely on the precise cancellation of terms derived from two separate circuits, one analog and one digital, and that there are added complexities on the digital sides. This thesis describes digital adaptive correction of nonidealities in dual-quantization and cascade modulators. The sources and effects of nonidealities in a first-order delta-sigma loop are analyzed. Simple correction schemes are presented, and theoretical SNR improvements are calculated and compared with simulation results. / Graduation date: 1993

Abstract not available