The number of devices and internet traffic for applications connected to the internet increases continuously. Devices provide increasing support for multi-homing and can utilize different access networks for end-to-end communication. The simultaneous use of multiple access networks can increase end-to-end performance by aggregating capacities from multiple disjoint networks by exploiting multipath communication. However, at this current point in time, multipath compatible transport layer protocols or multipath support at lower layers of the network stack have not seen widespread adaptation. Tunneled transport layer access bundling is an approach that allows for all types of single-path resources to exploit multipath communication by tunneling data over a Virtual Private Network (VPN) with transparent entry points on the User Equipment (UE) and on the internet. Commonly, such adaptation utilizes a single queue to buffer incoming packets which pose problems with fair multiplexing between concurrent application flows while being susceptible to bufferbloat. We designed and implemented extensions to Pluganized QUIC (PQUIC) which enables Flow Queuing Controlled Delay (FQ-CoDel) as a queueing discipline in tunneled transport layer access bundling to investigate if it is possible to achieve fair multiplexing between application flows while mitigating bufferbloat at the transport layer. An evaluation in the network emulator, mininet, shows that FQ-CoDel can add mechanisms for an instant, constant, and fair access to the VPN while significantly lowering the end-to-end latency for tunneled application flows. Furthermore, the results indicate that packet schedulers, such as Lowest-RTT-First (LowRTT) that adapt to current network characteristics, upholds the performance over heterogeneous networks while keeping the benefits of FQ-CoDel.

In the Internet of today there is a demand for both high bandwidth and low delays. Bandwidth-heavy applications such as large downloads or video streaming compete with more delay-sensitive applications; web-browsing, VoIP and video games. These applications represent a growing share of Internet traffic. Buffers are an essential part of network equipment. They prevent packet loss and help maintain hight throughput. As bandwidths have increased so have the buffer sizes. In some cases way to much. This, and the fact that Active Queue Management (AQM) is seldom implemented, has given rise to a phenomenon called Bufferbloat. Bufferbloat is manifested at the bottleneck of the network path by large flows creating standing queues that choke out smaller, and usually delay-sensitive, flows. Since the bottleneck is often located at the consumer edge, this is where the focus of this thesis lies. This work evaluates three different AQM solutions that lower delays without requiring complicated configuration; CoDel, FQ_CoDel and PIE. FQ_CoDel had the best performance in the tests, with the lowest consistent delays and high throughput. This thesis recommends that AQM is implemented at the network edge, preferably FQ_CoDel.

Power dissipation in CMOS circuits is of growing concern as the computational requirements of portable, battery operated devices increases. The ability to easily develop application specific circuits, rather than program general-purpose architectures can provide tremendous power savings. To this end, we present a design platform for rapidly developing power efficient hardware architectures starting at a system level. This high level VLSI design platform, called CoDeL, allows hardware description at the algorithm level, and thus dramatically reduces design time and power dissipation. We compare the CoDeL platform to a modern DSP and find that the CoDeL platform produces designs with somewhat slower run times but dramatically lower power dissipation. The CoDeL compiler produces an FSMD (Finite State Machine with Datapath) implementation of the circuit. This regular structure can be exploited to further reduce power through various techniques. To reduce dynamic power dissipation in the resulting architecture, the CoDeL compiler automatically inserts clock gating for registers. Power analysis shows that CoDeL's automated, high-level clock gating provides considerably more power savings than existing automated clock gating tools. To reduce static power, we use the CoDeL platform to analyze the potential and performance impact of power gating individual registers. We propose a static gating method, with very low area overhead, which uses the information available to the CoDeL compiler to predict, at compile time, when the registers can be powered off and powered on. Static branch prediction is used to more intelligently traverse the finite state machine description of the circuit to discover gating opportunities. Using simulation and estimation, we find that CoDeL with backward branch prediction gives the best overall combination of gating potential and performance. Compared to a dynamic time-based technique, this method gives dramatically more power savings, without any additional performance loss. Finally, we propose techniques to efficiently partition a FSMD using Integer Linear Programming and a simulated annealing approach. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated or power gated to achieve considerable power savings since only one processor is active at any given time. Implementation and estimation shows that significant power savings can be expected, when the original machine is partitioned into two or more submachines.