This thesis presents a design to route the spikes in a cognitive computing project called Systems of Neuromorphic Adaptive Plastic Scalable Electronics (SyNAPSE). SyNAPSE is a DARPA-funded program to develop electronic neuromorphic ma- chine technology that scales to biological levels. The basic computational block in the SyNAPSE system is the asynchronous spike processor (ASP) chip. This analog core contains the neurons and synapses in a neural fabric and performs the neural and synaptic computations.An ASP takes asynchronous pulses (spikes) as inputs and after some small delay produces asyn- chronous pulses as outputs.The ASP chips are organized in a nxn (where n [approximately equal to] 10) 2-dimensional grid with a dedicated node for each chip. This interconnected network is called Digital Fabric(DF) and the node is called Digital Fabric Node (DFN). The DF is a packet network that routes pulse (AER - Address event rep- resentation) packets between ASP's. This thesis also presents a technique for design implementation on a FPGA, perfor- mance testing of the network and validation of the network using various tools.