The currently used DSL splitters or filters are designed for ADSL band up to 1104 KHz and ADSL2+ band up to 2208 KHz. To meet faster internet access, DSL technology has evolved from ADSL into VDSL2 with an operating band up to 30 MHz. However, the splitters in VDSL2 band have some design difficulties in longitudinal conversion loss and isolation. The main purpose of this thesis is to find some solutions to overcome these design difficulties for splitters operating in VDSL2 band. The proposed solutions include the use of common-mode choke and compensation circuit. The final testing results of the splitters can validate the proposed solutions.

Recently, multimedia applications are used widely in many embedded and portable systems, such as mobile phones, MP3 player and PDA, which require lower power consumption within high performance constraints. Therefore, power-efficient design becomes a more important objective in Very Large Scale Integration (VLSI) designs. Moreover, the multiplication unit always lies on the critical path and ultimately determines the performance and power consumption of arithmetic computing systems. To achieve high-performance and lengthen the battery lifetime, it is crucial to develop a multiplier with high-speed and low power consumption. In multimedia and digital signal processing (DSP) applications, many low-power approaches have been presented to lessen the power consumption of multipliers by eliminating spurious computations. Moreover, the multiplication operations adopted in these systems usually allow accuracy loss to output data so as to achieve more power savings. Based on these conceptions, this dissertation considers input data characteristics and the arithmetic features of multiplications in various multimedia and DSP applications and presents novel power reduction and truncation techniques to design power-efficient multipliers and high-accuracy fixed-width multipliers. In the design of array and tree multipliers, we first propose a low power pipelined truncated multiplier which dynamically deactivates non-effective circuitry based on input range. Moreover, the proposed multiplier offers a flexible tradeoff between power reduction and product precision. This reconfigurable characteristic is very useful to systems which have different requirement on output precision. Second, a low-power configurable Booth multiplier that supports several multiplication modes and eliminates the redundant computations of sign bits in multipliers as much as possible is developed. This architecture can efficaciously decrease the power consumption of systems which demand computing performance and flexibility simultaneously. Although these two kinds of low power multipliers can achieve significant power savings, the hardware complexity of error compensation circuits and error performance in terms of the mean error and mean-square error are unsuitable for many multimedia systems composed of a large amount of multiply-accumulate operations. To efficiently improve the accuracy with less hardware complexity, we propose new error compensation circuits for fixed-width tree multipliers and fixed-width modified Booth multipliers. In the design of floating-point multipliers, we propose a low power variable-latency floating-point multiplier which is compliant with IEEE 754-1985 and suitable for 3-D graphics and multimedia applications. In the architecture, the significand multiplier is first partitioned into the upper and lower parts. Next, an efficient prediction scheme for the carry bit, sticky bit, and the upper part of significand product is developed. While the correct prediction occurs, the computation of lower part of significand multiplier is shut down and therefore the floating-point multiplication can consume less power and be completed early. In the design of modular multipliers, we propose an efficient modular multiplication algorithm to devise a high performance and low power modular multiplier. The proposed algorithm adopts the quotient pipelining and superfluous-operation elimination technique to discard the data dependency and redundant computational cycles of radix-2 Montgomery¡¦s multiplication algorithm so that the operation speed, power dissipation, and energy consumption of modular multipliers can be significantly improved.