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The traditional line stuck-at fault model does not properly represent transistor stuck-open (SOP) faults in complementary metal oxide semiconductor (CMOS) circuits. In general, test generation methods for detecting CMOS SOP faults are complex and time consuming due to the sequential behavior of faulty circuits. The majority of integrated circuit manufacturers still rely on stuck-at test sets to test CMOS combinational circuits at the risk of some SOP faults not being detected. In this thesis we investigate two aspects regarding the detection of SOP faults using stuck-at test sets. First, we measure the SOP fault coverage of stuck-at test sets for various CMOS combinational circuits. The SOP fault coverage is compared with that of random pattern test sets. Second, we propose a method to improve the SOP fault coverage of stuck-at test sets by organizing the test sequences of stuck-at test sets. The performance of the proposed method is compared with those of competing methods. Experimental results show that the proposed method leads to smaller test sets and shorter processing time while achieving high SOP fault coverage. / Master of Science

This dissertation explores the characteristics of Monotonic-Static CMOS and its potential applications in leakage reduction in ultra scaled Bulk-Si technology with significant gate leakage currents. Using test circuits consisting of different configurations of 16-bit lookahead adders, we performed a comparison among static, monotonic static and domino logic in terms of various properties including power, delay, noise margin and area. Comparisons were done over a wide range of possible transistor widths to fully characterize the tradeoffs for each circuit type. Experimental results show that MS-CMOS has potential advantages in some situations in terms of stand-by power, evaluation speed and noise margin in such a technology.

As advances in very large scale integration (VLSI) technology lead to higher levels of circuit integration and new design styles and fabrication processes, traditional test generation techniques fail to adequately address the problems of how to (l) accurately represent the structure of design styles and physical faults, and (2) manage the high computational costs and memory resource requirements caused by the complexity of VLSI. This research investigates a modular, hierarchical approach to test generation for combinational complementary metal oxide semiconductor (CMOS) circuits that effectively deals with these issues. Circuits are modeled using multi-level descriptions to handle large circuit sizes while maintaining an effective balance between accuracy and complexity. Object-oriented analysis and design techniques are used in the development of a hierarchical test generation application implemented using C++. In doing this, the primary objectives were to produce a easily maintainable system, provide an extensible framework for test generation supporting the straightforward incorporation of new types of circuit primitives and faults, and retain the same level of computational efficiency that can be achieved using a procedural language such as C. Characteristics of the object-oriented hierarchical test generation application, such as expandability and run-time efficiency, are compared to those of a standard gate-level test generation program implemented using C and a procedural design approach. / Ph. D.