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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Parallel implementation of an embedded run-time stack

Shallow, P. A. January 1999 (has links)
No description available.
2

A Template-Based Java Code Generator for OpenModelica and MetaModelica

Munisamy, Manokar January 2014 (has links)
The current OpenModelica Complier (OMC) translates Modelica models into executable Ccodethrough several stages. The Code Generator is the final stage of the compiler whichgenerates target C-code from the optimized sorted equations. Recently, the Code Generator inOMC has been rewritten using the OpenModelica text template language. This gives a moreconcise and easier to understand code generator. Modeling and simulation is becomingincreasingly used in several application areas. There is demand for the OpenModelicaComplier (OMC) to generate code in languages like C#, CSharp, XML, JAVA and so on. Inthis thesis work, we implement a Java code generator to translate the internal equation-basedmodels in OpenModelica and its extension MetaModelica into a Java code representation. Tocreate the Java code generator we used the OpenModelica text template language, also calledSusan. This work is an important step on the way to finalize a full version of a Java CodeGenerator for the OpenModelica Complier (OMC).
3

Enhancing productivity and performance portability of OpenCL applications on heterogeneous systems using runtime optimizations

Lutz, Thibaut January 2015 (has links)
Initially driven by a strong need for increased computational performance in science and engineering, heterogeneous systems have become ubiquitous and they are getting increasingly complex. The single processor era has been replaced with multi-core processors, which have quickly been surrounded by satellite devices aiming to increase the throughput of the entire system. These auxiliary devices, such as Graphics Processing Units, Field Programmable Gate Arrays or other specialized processors have very different architectures. This puts an enormous strain on programming models and software developers to take full advantage of the computing power at hand. Because of this diversity and the unachievable flexibility and portability necessary to optimize for each target individually, heterogeneous systems remain typically vastly under-utilized. In this thesis, we explore two distinct ways to tackle this problem. Providing automated, non intrusive methods in the form of compiler tools and implementing efficient abstractions to automatically tune parameters for a restricted domain are two complementary approaches investigated to better utilize compute resources in heterogeneous systems. First, we explore a fully automated compiler based approach, where a runtime system analyzes the computation flow of an OpenCL application and optimizes it across multiple compute kernels. This method can be deployed on any existing application transparently and replaces significant software engineering effort spent to tune application for a particular system. We show that this technique achieves speedups of up to 3x over unoptimized code and an average of 1.4x over manually optimized code for highly dynamic applications. Second, a library based approach is designed to provide a high level abstraction for complex problems in a specific domain, stencil computation. Using domain specific techniques, the underlying framework optimizes the code aggressively. We show that even in a restricted domain, automatic tuning mechanisms and robust architectural abstraction are necessary to improve performance. Using the abstraction layer, we demonstrate strong scaling of various applications to multiple GPUs with a speedup of up to 1.9x on two GPUs and 3.6x on four.
4

Predictors of Attendance and the Impact of Attendance on Outcomes for a Parenting Programme in Two Southeast Asian Countries

Janowski, Roselinde Katharina 29 January 2021 (has links)
Background: Children living in low- and middle-income countries (LMICs) experience alarmingly high rates of maltreatment, frequently at the hands of caregivers. Group-based parenting programmes show promise for reducing and preventing child maltreatment, as well as for improving positive parenting, child behaviour problems, and caregiver mental health. However, parenting programmes can only benefit families if caregivers participate in them. Using secondary data, this study thus aimed to 1) identify factors that affect attendance and 2) investigate the impact of attendance on outcomes within two randomised controlled trials of Parenting for Lifelong Health (PLH) for Young Children for caregivers of children aged 2-9 years in Thailand (N = 120) and 2-6 years in the Philippines (N = 120). The interventions were delivered within existing service delivery systems in both countries, over eight weekly sessions (Thailand) or 12 sessions every second week (Philippines). Method: To address the first aim of this study, multivariable logistic regression models with robust sandwich estimators were used to examine family baseline characteristic as predictors of caregiver attendance in sessions. An exploratory approach was taken to test a range of factors that have previously been linked to attendance in parenting programmes, including economic and educational, social and health, parenting and child behaviour, and sociodemographic characteristics. To address the second aim, caregiver self-reports and observational assessments (Thailand only) from baseline, post-test, and follow-up were analysed using complier average causal effect (CACE) analyses to test the impact of attendance variability on the primary outcomes of child maltreatment, as well as secondary outcomes of positive parenting, dysfunctional parenting, child behaviour problems, and caregiver mental health. Results: Caregivers in Thailand attended 82.3% of sessions while those in the Philippines attended 61.8%. Overall, few baseline factors were significantly associated with attendance. In Thailand, caregivers who were less educated and those who were older were significantly more likely to attend sessions. In the Philippines, caregivers who were less healthy, those that who used more emotional abuse, and those who had boys rather than girls were significantly more likely to attend. Notably, caregivers who experienced higher rates of intimate partner violence significantly attended 8% fewer sessions in the Philippines. A comparison of CACE estimates to intention-to-treat estimates at post-test and at follow-up showed greater benefits of the intervention amongst caregivers who attended more sessions. Specifically, the strongest intervention effects were found for caregivers who attended at least 75% of the programme. Conclusion: This study showed no evidence that disadvantages related to lower socio-economic status were associated with attendance, suggesting that it is possible for vulnerable families in LMICs to attend parenting programmes. However, developing retention strategies that target subgroups who are at greater risk of missing sessions is especially important as higher attendance at sessions is positively related to greater improvements in caregiver and child outcomes.
5

A C to Register Transfer Level Algorithm Using Structured Circuit Templates: A Case Study with Simulated Annealing

Phillips, Jonathan D. 01 December 2008 (has links)
A tool flow is presented for deriving simulated annealing accelerator circuits on a field programmable gate array (FPGA) from C source code by exploring architecture solutions that conform to a preset template through scheduling and mapping algorithms. A case study carried out on simulated annealing-based Autonomous Mission Planning and Scheduling (AMPS) software used for autonomous spacecraft systems is explained. The goal of the research is an automated method for the derivation of a hardware design that maximizes performance while minimizing the FPGA footprint. Results obtained are compared with a peer C to register transfer level (RTL) logic tool, a state-of-the-art space-borne embedded processor and a commodity desktop processor for a variety of problems. The automatically derived hardware circuits consistently outperform other methods by one or more orders of magnitude.
6

Compilation For Intrusion Detection Systems

Lydon, Andrew 25 June 2004 (has links)
No description available.

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