Spelling suggestions: "subject:"computer arithmetic"" "subject:"computer rithmetic""
1 |
Design issues for accurate and reliable arithmetic /Stine, James E. January 2000 (has links)
Thesis (Ph. D.)--Lehigh University, 2000. / Includes vita. Includes bibliographical references (leaves 149-169).
|
2 |
Instruction set enhancements for reliable computations /Akkaş, Ahmet, January 2001 (has links)
Thesis (Ph. D.)--Lehigh University, 2001. / Includes vita. Includes bibliographical references (leaves 131-141).
|
3 |
Novel algorithms and architectures for multiplicationMekhallalati, Mejahed C. January 1997 (has links)
No description available.
|
4 |
Integer multiplier and squarer architectures with overflow detection /Gök, Mustafa, January 2003 (has links)
Thesis (Ph. D.)--Lehigh University, 2004. / Includes vita. Includes bibliographical references (leaves 205-221).
|
5 |
Saturating arithmetic for digital signal processors /Balzola, Pablo I. January 2003 (has links)
Thesis (Ph. D.)--Lehigh University, 2003. / Includes vita. Includes bibliographical references (leaves 125-136).
|
6 |
Improved algorithms for non-restoring division and square rootJun, Kihwan 22 February 2013 (has links)
This dissertation focuses on improving the non-restoring division and square root algorithm. Although the non-restoring division algorithm is the fastest and has less complexity among other radix-2 digit recurrence division algorithms, there are some possibilities to enhance its performance. To improve its performance, two new approaches are proposed here. In addition, the research scope is extended to seek an efficient algorithm for implementing non-restoring square root, which has similar steps to non-restoring division. For the first proposed approach, the non-restoring divider with a modified algorithm is presented. The new algorithm changes the order of the flowchart, which reduces one unit delay of the multiplexer per every iteration. In addition, a new method to find a correct quotient is presented and it removes an error that the quotient is always odd number after a digit conversion from a digit converter from the quotient with digits 1 and -1 to conventional binary number. The second proposed approach is a novel method to find a quotient bit for every iteration, which hides the total delay of the multiplexer with dual path calculation. The proposed method uses a Most Significant Carry (MSC) generator, which determines the sign of each remainder faster than the conventional carry lookahead adder and it eventually reduces the total delay by almost 22% compared to the conventional non-restoring division algorithm. Finally, an improved algorithm for non-restoring square root is proposed. The two concepts already applied to non-restoring division are adopted for improving the performance of a non-restoring square root since it has similar process to that of non-restoring division for finding square root. Additionally, a new method to find intermediate quotients is presented that removes an adder per an iteration to reduce the total area and power consumption. The non-restoring square root with MSC generator reduces total delay, area and power consumption significantly. / text
|
7 |
A CORDIC arithmetic processor /Wang, Shaoyun, January 1998 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 1998. / Vita. Includes bibliographical references (leaves 128-135). Available also in a digital version from Dissertation Abstracts.
|
8 |
Error analysis of summation taking into account computer characteristics, specific programming system, and data qualityGutterman, Peter Andrew. January 1978 (has links)
Thesis--Wisconsin. / Vita. Includes bibliographical references (leaves 392-400).
|
9 |
A Stream-Based In-Line Allocatable Multiplier for Configurable ComputingYang, Tsung-Han 05 September 1997 (has links)
The growing demand for high-performance computing platforms has pushed the computing community to invent new architectures for processors. Recently, researchers have begun to solve the problem by the implementation of Field-Programming Gate Arrays (FPGAs). FPGAs make it possible to implement different applications on the same hardware. Unfortunately, FPGAs suffer from low bandwidth, density, and throughout. To gain the flexibility of FPGAs and to gain more computational capacity than conventional processors have, Wormhole run-time reconfigurable (RTR) techniques has been developed to address some high performance digital signal processing (DSP) problems.
Multiplication is one of the basic functions used in digital signal processing. Most high-performance DSP systems rely on hardware multiplication to achieve high data throughput. To meet the processing needs of DSP, a multiplier was embedded into a prototype wormhole RTR device called Colt, but because each design has its own speed and size requirements, rarely can a designer take an already existing multiplier module and use it in Colt. Therefore redesigning multipliers is necessary for meeting the system specifications of Colt. This thesis explores the design of the multiplier from architecture level to circuit level. / Master of Science
|
10 |
"a+b" arithmetic theory and implementation.Manickavasagam, SenthilKumar. January 1996 (has links)
Thesis (M.S.)--Ohio University, March, 1996. / Title from PDF t.p.
|
Page generated in 0.0729 seconds