Regardless of the numeric base, scientific notation breaks numbers into three parts: sign, mantissa, and exponent. In this episode, we discuss how the computer stores those three parts to memory, and why IEEE 754 puts them together the way it does.

ASCII was developed when every computer was an island and over 35 years before the first emoji appeared. In this episode, we will take a look at how Unicode and UTF-8 expanded ASCII for ubiquitous use while maintaining backwards compatibility.

To make the move to a four-variable Karnaugh map, we are going to double the number of columns found in the three-variable map. And what happens when we halve the three-variable map? We get a two-variable Karnaugh map!

Sometimes, it’s nice to take a look at old tech to learn a new tool. The 7-segment display has been in our lives for years – mostly in alarm clocks. Join us as we use a Karnaugh map to design a driver for one.

Inverting or flipping the bits of an integer is the third and last method of “bit bashing” we will discuss. There are two ways to invert bits: either flip all of them at once or use a mask to identify which bits to flip and which to leave alone.

<p> A user-oriented computer program for an optimum solution of the hydrodynamic journal bearings is developed. The computer package is formulated in such a way to determine the optimum solution using only any of the following optimization techniques adapted from OPTISEP: DAVID, SIMPLEX, SEEK1, AND SEEK3. </p> <p> A user guide and a complete documentations for the computer package are included in the thesis. </p> / Thesis / Master of Engineering (ME)

<p>The challenge of building scalable quantum computer lies in striking appropriate balance between designing a reliable system architecture from large number of faulty computational resources and improving the physical quality of system components. The detailed investigation of performance variation with physics of the components and the system architecture requires adequate performance simulation tool. In this thesis we demonstrate a software tool capable of (1) mapping and scheduling the quantum circuit on a realistic quantum hardware architecture with physical resource constraints, (2) evaluating the performance metrics such as the execution time and the success probability of the algorithm execution, and (3) analyzing the constituents of these metrics and visualizing resource utilization to identify system components which crucially define the overall performance.</p><p>Using this versatile tool, we explore vast design space for modular quantum computer architecture based on trapped ions. We find that while success probability is uniformly determined by the fidelity of physical quantum operation, the execution time is a function of system resources invested at various layers of design hierarchy. At physical level, the number of lasers performing quantum gates, impact the latency of the fault-tolerant circuit blocks execution. When these blocks are used to construct meaningful arithmetic circuit such as quantum adders, the number of ancilla qubits for complicated non-clifford gates and entanglement resources to establish long-distance communication channels, become major performance limiting factors. Next, in order to factorize large integers, these adders are assembled into modular exponentiation circuit comprising bulk of Shor's algorithm. At this stage, the overall scaling of resource-constraint performance with the size of problem, describes the effectiveness of chosen design. By matching the resource investment with the pace of advancement in hardware technology, we find optimal designs for different types of quantum adders. Conclusively, we show that 2,048-bit Shor's algorithm can be reliably executed within the resource budget of 1.5 million qubits.</p> / Dissertation