No description available.

No description available.

No description available.

No description available.

No description available.

Algorithms used to determine the control and data flow properties of computer programs are generally designed for one-time analysis of an entire new input. Application of such algorithms when the input is only slightly modified results in an inefficient system. In this theses a set of incremental update algorithms are presented for data flow analysis. These algorithms update the solution from a previous analysis to reflect changes in the program. Thus, extensive reanalysis to reflect changes in the program. Thus, extensive reanalysis of programs after each program modification can be avoided. The incremental update algorithms presented for global flow analysis are based on Hecht/Ullman iterative algorithms. Banning's interprocedural data flow analysis algorithms form the basis for the incremental interprocedural algorithms.

The system described in this research report computes 1975 Federal income tax for those who itemize deductions. The system user calls the program, written in FORTRAN IV, from a computer terminal, and then types answers to questions asked by the program. The user is given the opportunity to make corrections in the answers, and then the system calculates and prints out information necessary the complete IRS Form 1040 and Schedule A. The paper contains a description of the system, and explanation of the program, recommendations for future revision, and suggestions for expansion of the system. Four appendices contain IRS Form 1040 and Schedule A, sample cases, a complete program listing, and the gas tax and sales tax tables and tax rates schedules X, Y, and Z in which the tax is found.

In this paper, hardware and software techniques are presented for improving the Throughput (defined as computations per dollar) of computing systems which are oriented towards high-precision floating point computations. The various improvements are referenced to a baseline of the PDP 11/20, the NOVA 1200, and the TI 960A, all 16 bit minicomputers. The most beneficial hardware improvement is the inclusion of a Floating Point Processor, which yields up to 200X Throughput increase over a software floating point package. The inclusion of a cache high speed local memory and the availability of Polish Notation format instructions are shown to provide less than a 5X increase each. The use of 48 bit data paths, numerous registers devoted to various processor functions, instruction look ahead, a system I/O controller which frees the processor from I/O work, and partitioned main memory, result in a combined Throughput increase of 5.9X.

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Nuclear Engineering, 1977 / Vita. / Includes bibliographical references. / Ph. D. / Ph. D. Massachusetts Institute of Technology, Department of Nuclear Engineering

No description available.