Thesis (M.S.)--University of Louisville, 2004. / Department of Electrical Engineering. Vita. "May 2004." Includes bibliographical references (leaf 51).

No description available.

Thesis (Ph. D.)--Lehigh University, 2004. / Includes vita. Includes bibliographical references (leaves 153-167).

Typescript (photocopy). / Digitized by Kansas Correctional Industries

Custom hardware accelerators are commonly used in simulation systems requiring high computational power. Such applications often have few data dependencies, allowing implementation using parallel datapaths. For such problems, optimization of the datapath of the circuits leads to significant improvements in overall performance. / The Computer Arithmetic Synthesis Technology (CAST) framework, developed in this work, allows one to quickly explore the design space in three dimensions: the number system, the operator architecture and the configuration of individual operators. It utilizes sophisticated arithmetic algorithms and reconfigurable architectures, captured in the object libraries. The final result is an optimized datapath satisfying user requirements, and the output can be controlled at different levels. / To demonstrate its ability, the CAST framework is used to implement a number of simulation systems including the datapath for the force computation pipeline of N-body simulation and Monte Carlo simulation for interest rate financial derivatives. A novel multiplier generator and an efficient random number generator are also presented as basic building blocks for simulation. Together, these tools provide an easy way to describe simulation system in a number system independent manner, and generate implementation to satisfy different performance, area and accuracy constraints. / Tsoi Kuen Hung. / "November 2007." / Adviser: Philip H. W. Leong. / Source: Dissertation Abstracts International, Volume: 69-08, Section: B, page: 4862. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (p. 106-118). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Ho Chun Hok. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 74-78). / Abstracts in English and Chinese. / Abstract --- p.ii / Acknowledgement --- p.v / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Aims --- p.3 / Chapter 1.3 --- Contributions --- p.3 / Chapter 1.4 --- Thesis Organization --- p.4 / Chapter 2 --- Background and Literature Review --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- Field Programmable Gate Arrays --- p.5 / Chapter 2.3 --- Traditional design flow and VHDL --- p.6 / Chapter 2.4 --- Single Description for Hardware-Software Systems --- p.7 / Chapter 2.5 --- Parameterized Floating Point Arithmetic Implementation --- p.8 / Chapter 2.6 --- Function Approximations by Table Lookup and Addition --- p.9 / Chapter 2.7 --- Summary --- p.10 / Chapter 3 --- Floating Point Arithmetic --- p.11 / Chapter 3.1 --- Introduction --- p.11 / Chapter 3.2 --- Floating Point Number Representation --- p.11 / Chapter 3.3 --- Rounding Error --- p.12 / Chapter 3.4 --- Floating Point Number Arithmetic --- p.14 / Chapter 3.4.1 --- Addition and Subtraction --- p.14 / Chapter 3.4.2 --- Multiplication --- p.17 / Chapter 3.5 --- Summary --- p.17 / Chapter 4 --- FLY - Hardware Compiler --- p.18 / Chapter 4.1 --- Introduction --- p.18 / Chapter 4.2 --- The Fly Programming Language --- p.18 / Chapter 4.3 --- Implementation details --- p.19 / Chapter 4.3.1 --- Compilation Technique --- p.19 / Chapter 4.3.2 --- Statement --- p.21 / Chapter 4.3.3 --- Assignment --- p.21 / Chapter 4.3.4 --- Conditional Branch --- p.22 / Chapter 4.3.5 --- While --- p.22 / Chapter 4.3.6 --- Parallel Statement --- p.22 / Chapter 4.4 --- Development Environment --- p.24 / Chapter 4.4.1 --- From Fly to Bitstream --- p.24 / Chapter 4.4.2 --- Host Interface --- p.24 / Chapter 4.5 --- Summary --- p.26 / Chapter 5 --- Float - Floating Point Design Environment --- p.27 / Chapter 5.1 --- Introduction --- p.27 / Chapter 5.2 --- Floating Point Tools --- p.28 / Chapter 5.2.1 --- Float Class --- p.29 / Chapter 5.2.2 --- Optimization --- p.31 / Chapter 5.3 --- Digital Sine-Cosine Generator --- p.33 / Chapter 5.4 --- VHDL Floating Point operator generator --- p.35 / Chapter 5.4.1 --- Floating Point Multiplier Module --- p.35 / Chapter 5.4.2 --- Floating Point Adder Module --- p.36 / Chapter 5.5 --- Application to Solving Differential Equations --- p.38 / Chapter 5.6 --- Summary --- p.40 / Chapter 6 --- Function Approximation using Lookup Table --- p.42 / Chapter 6.1 --- Table Lookup Approximations --- p.42 / Chapter 6.1.1 --- Taylor Expansion --- p.42 / Chapter 6.1.2 --- Symmetric Bipartite Table Method (SBTM) --- p.43 / Chapter 6.1.3 --- Symmetric Table Addition Method (STAM) --- p.45 / Chapter 6.1.4 --- Input Range Scaling --- p.46 / Chapter 6.2 --- VHDL Extension --- p.47 / Chapter 6.3 --- Floating Point Extension --- p.49 / Chapter 6.4 --- The N-body Problem --- p.52 / Chapter 6.5 --- Implementation --- p.54 / Chapter 6.6 --- Summary --- p.56 / Chapter 7 --- Results --- p.58 / Chapter 7.1 --- Introduction --- p.58 / Chapter 7.2 --- GCD coprocessor --- p.58 / Chapter 7.3 --- Floating Point Module Library --- p.59 / Chapter 7.4 --- Digital sine-cosine generator (DSCG) --- p.60 / Chapter 7.5 --- Optimization --- p.62 / Chapter 7.6 --- Ordinary Differential Equation (ODE) --- p.63 / Chapter 7.7 --- N Body Problem Simulation (Nbody) --- p.63 / Chapter 7.8 --- Summary --- p.64 / Chapter 8 --- Conclusion --- p.66 / Chapter 8.1 --- Future Work --- p.68 / Chapter A --- Fly Formal Grammar --- p.70 / Chapter B --- Original Fly Source Code --- p.71 / Bibliography --- p.74

Typescript (photocopy). / Digitized by Kansas Correctional Industries

Computer and network security has recently become a popular subject due to the explosive growth of the Internet and the migration of commerce practices to the electronic medium. Thus the authenticity and privacy of the information transmitted and the data stored on networked computers is of utmost importance. The deployment of network security procedures requires the implementation of cryptographic functions. More specifically, these include encryption, decryption, authentication, digital signature algorithms and message-digest functions. Performance has always been the most critical characteristic of a cryptographic function, which determines its effectiveness. In this thesis, we concentrate on developing high-speed algorithms and architectures for number theoretic cryptosystems. Our work is mainly focused on implementing elliptic curve cryptosystems efficiently, which requires space- and time-efficient implementations of arithmetic operations over finite fields. We introduce new methods for arithmetic operations over finite fields. Methodologies such as precomputation, residue number system representation, and parallel computation are adopted to obtain efficient algorithms that are applicable on a variety of cryptographic systems and subsystems. Since arithmetic operations in finite fields also have applications in coding theory and computer algebra, the methods proposed in this thesis are applicable to these applications as well. / Graduation date: 1999

Thesis (M.F.A.)--Rochester Institute of Technology, 2007. / Typescript. Includes bibliographical references (leaf 38).

Thesis (Ph. D.)--Lehigh University, 2000. / Includes vita. Includes bibliographical references (leaves 135-142).