In the growing field of digital system design, there is a great need for design tools that will assist the engineer in developing large scale systems. AHPL, A Hardware Programming Language, is a hardware description language which allows a digital system to be described, evaluated, and analyzed. But like many design tools, AHPL cannot satisfy the multitude of design tool applications. In order to enhance the power of AHPL as a design tool, an EDIF translator is developed. The EDIF translator generates an EDIF netlist of an AHPL design, thus making it possible to port AHPL designs to other design tools.

In this research, an AHPL (A Hardware Programming Language) based automation system is used to design and verify the Intel-8080 microprocessor from the RTL (Register Transfer Level) hardware description through the network list of transistors. The HPSIM is used as a RTL simulator which interprets the AHPL description and executes the connections, branches, and register transfer, and prints line or register values for each circuit clock period. After the AHPL description has been translated to switch-level link list, ESIM is applied for more detailed simulation to ensure the digital behavior in this microprocessor design is correct. The ESIM is an event-driven switch-level simulator which accepts commands from the user, and executes each command before reading the next one. After performing these different levels of simulations, a comparison is discussed at the end.

The use of Computer Hardware Description Languages plays an important role in the design automation process of digital systems. These languages help hardware engineers to provide a precise description of the internal structure of a system, and one of the most significant uses of these languages is as a means of input to a system simulator. AHPL is a hardware description language that describes a digital system as a set of modules and units. This language is supported by a function-level simulator (HPSIM2), but the simulator only provides support to the module descriptions of a system. This paper presents an improved version of the simulator that supports the use of unit descriptions called Combinational Logic Units or CLUNITs. The syntax and structure of a CLUNIT is analyzed, the operation and data structure of the simulator is given; and several examples are given to support these discussions.

No description available.

Thesis (M.Eng.)--Memorial University of Newfoundland, 2001. / Restricted until June 2002. Bibliography: leaves 96-98.

Thesis (Ph. D.)--University of Texas at Dallas, 2007. / Includes vita. Includes bibliographical references (leaves 201-214)

The Internet has grown in popularity in recent years, and thus it has gained importance for many current businesses. They need to offer their products and services through their Web sites. To present not only static content but also interactive services, the logic behind these services needs to be programmed. Various approaches for programming Web services exist. The Java programming language can be used to implement Web services that run both on Internet clients and servers, either exclusively or in interaction with each other. The Java programming language is standardised across computing platforms and has matured over the past few years, and is therefore a popular choice for the implementation of Web services. The amount of available and well-tested Java source code is still small compared to other programming languages. Rather than taking the risks and costs of redeveloping program libraries, it is often preferable to move the core logic of existing solutions to Java and then integrate it into Java programs that present the services in a Web interface. In this Ph.D. dissertation, we survey and evaluate a selection of current approaches to the migration of source code to Java. To narrow the scope of the dissertation to a reasonable limit, we focus on the C and C++ programming languages as the source languages. Many mature programs and program libraries exist in these languages. The survey of current migration approaches reveals a number of their restrictions and disadvantages in the context of moving program libraries to Java and integrating them with Java programs. Using the experiences from this survey, we established a number of goals for an improved migration approach and developed the Ephedra approach by closely following these goals. To show the practicality of this approach, we implemented an automated tool that performs the migration according to the Ephedra approach and evaluated the migration process and its result with respect to the goals we established using selected case studies. Ephedra provides a high degree of automation for the migration process while letting the software-engineer make decisions where multiple choices are possible. A central problem in the migration from C to Java is the trans formation of C pointers to Java references. Ephedra provides two different strategies for this transformation and explains their applicability to subject systems. The code resulting from a migration with Ephedra is maintainable and functionally equivalent to the original code save some well documented exceptions. Performance trade-offs are analysed and evaluated in the light of the intended subject systems. / Graduate

In order to increase productivity, methodologies based on reuse of previously designed components are exploited by the Integrated Circuit (IC) design community. However, designers are often faced with the problem of reusing a legacy design for which the behavior is unclear due to missing documentation and the complexity of the design. In this dissertation a methodology to assist designers in retrieving the original intent of a design from its Hardware Description Language (HDL) specification is described. The methodology is based on code analysis and techniques which produce different views of HDL code. These views represent the behavior of a design in more abstract terms than the HDL code. / Graduate

Thesis (Ph. D.)--Oregon Graduate Institute, 2000.

We present the first dynamic algorithm that maintains a clique tree representation of a chordal graph and supports the following operations: (1) query whether deleting or inserting an arbitrary edge preserves chordality, (2) delete or insert an arbitrary edge, provided it preserves chordality. We give two implementations. In the first, each operation runs in O( n) time, where n is the number of vertices. In the second, an insertion query runs in O(log² n) time, an insertion in O(n) time, a deletion query in O(n) time, and a deletion in O(n log n) time. We also introduce the clique-separator graph representation of a chordal graph, which provides significantly more information about the graph's structure than the well-known clique tree representation. We present fundamental properties of the clique-separator graph and additional properties when the input graph is interval. We then introduce the train tree representation of interval graphs and use it to decide whether there is a certain linear ordering of the graph's maximal cliques. This yields a fully dynamic algorithm to recognize interval graphs in O(n log n) time per edge insertion or deletion. The clique-separator graph may lead to dynamic algorithms for every proper subclass of chordal graphs, and the train tree may lead to fast dynamic algorithms for problems on interval graphs. / Graduate