Thesis (M.S.)--University of Hawaii at Manoa, 2007. / Includes bibliographical references (leaves 71-74). / xi, 74 leaves, bound ill. 29 cm

This thesis describes a new simulation technique, Synchronous Faults Simulation by Surrogate with Exception, first proposed by Dr. F. J. Hill and has been initiated under the direction of Xiolin Wang. This paper reports early results of that project. The Sequential Circuit Test Sequence System, SCIRTSS, is an automatic test generation system which is developed in University of Arizona which will be used as a target to compare against the results of the new simulator. The major objective of this research is to analyze the results obtained by using the new simulator SFSSE against the results obtained by using the parallel simulator SCIRTSS. The results are listed in this paper to verify superiority of the new simulation technique.

Thesis (M. Sc.)--Carleton University, 2003. / Includes bibliographical references (p. 95-98). Also available in electronic format on the Internet.

No description available.

Thesis (M.Sc.) - Carleton University, 2005. / Includes bibliographical references (p. 106-111). Also available in electronic format on the Internet.

The performance of SPICE and Network C (NC) circuit simulator when simulating MOS transistor circuits has been investigated and compared. SPICE analog model, NC analog model and NC MOS_PWL model are the three MOS transistor models being used. The comparison between SPICE and NC includes five areas. They are MOS transistor model, circuit analysis and computational methods, limitation on the ability to simulate circuits containing the MOS transistor diode configuration, run time and the ability to build new circuit component models using derived equations.

A methodology is proposed for designing performance optimized computer systems. The methodology uses software tools created for performance monitoring and evaluation of parallel programs, replacing actual hardware with a simulator modeling the hardware under development. We claim that a software environment can help hardware designers to make decisions on the architectural design level. A simulator executes real programs and provides access to performance monitors from user's code. The performance monitoring system collects data traces when running the simulator and the performance analysis module extracts performance data of interest, that are later displayed with visualization tools. Key features of our methodology are "plug and play" simulation and modeling hardware/software interaction during the process of hardware design. The ability to use different simulators gives the user flexibility to configure the system for the required functionality, accuracy and simulation performance. Evaluation of hardware performance based on results obtained by modeling hardware/software interaction is crucial for designing performance optimized computer systems. We have developed a software system, based on our design methodology, for performance evaluation of multicomputer interconnection networks. The system, called the Parsim Common Environment (PCE), consists of an instrumented network simulator that executes assembly language instructions, and performance analysis and visualization modules. Using PCE we have investigated a specific network design example. The system helped us spot performance problems, explain why they happened and find the ways to solve them. The obtained results agreed with observations presented in the literature, hence validating our design methodology and the correctness of the software performance evaluation system for hardware designs. Using software tools a designer can easily check different design options and evaluate the obtained performance results without the overhead of building expensive prototypes. With our system, data analysis that required 10 man-hours to complete manually took just a couple of seconds on a Sparc-4 workstation. Without experimentation with the simulator and the performance evaluation environment one might build an expensive hardware prototype, expecting improved performance, and then be disappointed with poorer results than expected. Our tools help designers spot and solve performance problems at early stages of the hardware design process.

Thesis (M.C.S.) - Carleton University, 2005. / Includes bibliographical references (p. 260-271). Also available in electronic format on the Internet.

Simulation is one of the most important tools for system performance evaluation in communication networks as well as many other areas. However, simulation is computationally intensive. A traditional sequential simulation of a complex model or a rare-event system may require days or even weeks of computer execution time. Therefore, simulation often becomes a bottleneck of a performance study. With the growing availability of multiprocessor computing systems (e.g., tightly-coupled parallel computers or distributed networks of workstations), parallel simulation, which parallelizes a simulation program for execution on multiple processors, becomes an attractive means to reduce simulation execution time. With few exceptions, existing parallel simulation algorithms can be broadly classified into four methods: multiple replication, time-parallel, parallel regenerative, and space-parallel. Each method is associated with some advantages and limitations. We study these methods and propose a number of parallel simulation algorithms for a class of communication network systems modeled by queueing systems. In multiple replication simulation, each processor simulates a replication of the target simulation model independently. Due to the lack of a prior: knowledge about the steady state conditions, an arbitrarily selected initial state is often used for each simulation run. This can result in significant bias in the simulation outcome. To reduce this initial transient bias, we propose a polling initialization technique, in which a pilot simulation is used to find 'good' initial states that are representative of the steady-state conditions. Time-parallel simulation obtains parallelism by partitioning the time domain of the simulation model into a number of batches. Each batch is computed by a processor independently. Time-parallel simulation has not been fully explored by the research community partly because finding the exact initial states for the batches is often challenging and problem dependent. We develop two approximation time-parallel simulation algorithms for acyclic networks of loss G/G/1/K and G/D/1/K queues. These algorithms exploit unbounded parallelism and can achieve near-linear speedup when the number of arrivals is large. Two other time-parallel approaches are also proposed for Markov chains. For more general simulation models, an approximation approach that uses a substate matching technique is presented. Parallel regenerative simulation exploits parallels in by partitioning the simulation trajectory into a number of regeneration cycles. The amount of parallelism relies on the regeneration frequency of the model. In practice a regeneration state that has a short expected regeneration cycle length often does not exist in the target simulation model. As a result, a sufficient number of observations can not be obtained in a finite simulation interval. To overcome this constraint, we propose a partial regeneration algorithm that uses a substate matching technique to increase the number of observations. When the memory requirement of the target simulation models exceeds the storage capacity of a single processor, space-parallel simulation is an appropriate method. In space-parallel simulation, the target simulation model is decomposed into a number of components such that each component contains a disjoint subset of the model state variables. Each component is mapped into a logical process which is responsible for computing the trajectory corresponding to the component over the simulation time interval. An important class of space-parallel simulation is the conservative simulation, in which each logical process can proceed processing an event only if the process ensures that no event. will arrive later with a smaller timestamp. A number of previous experimental studies have suggested that lookahead, a capability that allows a simulation to look into the simulation time future, plays an important role in the performance of the conservative simulation. Although the performance of conservative simulation has been the interest in many previous studies, there has been a lack of formal arguments to quantify the impact of lookahead to conservative simulation performance. To address this question, we develop stochastic models to study the relationship between the amount of lookahead and the simulation performance with respect to different model topologies. We show that for closed simulation models, the simulation execution time is proportional to the amount of lookahead. For open models, on the other hand, lookahead is effectively useless when the simulation length is long. / Ph. D.

The research described in this thesis is divided conveniently into three components: (1) the credibility assessment of a simulation model for the investigation of dynamically reconfigurable computer network architectures, (2) a comparative study of the standardized time series method of simulation output analysis, and (3) an experimental comparison of the effects of dynamic reconfigurability on message transmission delays and network throughput. The credibility assessment relies almost completely on verification procedures applied to both communicative and program representations of the model. In the absence of an extant system, validation consists of extensive, program traces to assure that model behavior matches expectations and reflects no inconsistencies. Application of a standardized time series technique produces the advantages reported by other researchers with regard to sampling efficiency (information derived per sample unit) when dynamic reconfigurability is precluded. The inherent non-stationarity induced by reconfiguration reveals the sensitivity of standardized time series and the consequent adjustment to preserve coverage. A compromise between coverage and sampling efficiency prompts the choice of the batch means method for experimental comparison. Experimental comparison shows that under high traffic variability reconfigurability / Master of Science