Ho Chun Hok. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 74-78). / Abstracts in English and Chinese. / Abstract --- p.ii / Acknowledgement --- p.v / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Aims --- p.3 / Chapter 1.3 --- Contributions --- p.3 / Chapter 1.4 --- Thesis Organization --- p.4 / Chapter 2 --- Background and Literature Review --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- Field Programmable Gate Arrays --- p.5 / Chapter 2.3 --- Traditional design flow and VHDL --- p.6 / Chapter 2.4 --- Single Description for Hardware-Software Systems --- p.7 / Chapter 2.5 --- Parameterized Floating Point Arithmetic Implementation --- p.8 / Chapter 2.6 --- Function Approximations by Table Lookup and Addition --- p.9 / Chapter 2.7 --- Summary --- p.10 / Chapter 3 --- Floating Point Arithmetic --- p.11 / Chapter 3.1 --- Introduction --- p.11 / Chapter 3.2 --- Floating Point Number Representation --- p.11 / Chapter 3.3 --- Rounding Error --- p.12 / Chapter 3.4 --- Floating Point Number Arithmetic --- p.14 / Chapter 3.4.1 --- Addition and Subtraction --- p.14 / Chapter 3.4.2 --- Multiplication --- p.17 / Chapter 3.5 --- Summary --- p.17 / Chapter 4 --- FLY - Hardware Compiler --- p.18 / Chapter 4.1 --- Introduction --- p.18 / Chapter 4.2 --- The Fly Programming Language --- p.18 / Chapter 4.3 --- Implementation details --- p.19 / Chapter 4.3.1 --- Compilation Technique --- p.19 / Chapter 4.3.2 --- Statement --- p.21 / Chapter 4.3.3 --- Assignment --- p.21 / Chapter 4.3.4 --- Conditional Branch --- p.22 / Chapter 4.3.5 --- While --- p.22 / Chapter 4.3.6 --- Parallel Statement --- p.22 / Chapter 4.4 --- Development Environment --- p.24 / Chapter 4.4.1 --- From Fly to Bitstream --- p.24 / Chapter 4.4.2 --- Host Interface --- p.24 / Chapter 4.5 --- Summary --- p.26 / Chapter 5 --- Float - Floating Point Design Environment --- p.27 / Chapter 5.1 --- Introduction --- p.27 / Chapter 5.2 --- Floating Point Tools --- p.28 / Chapter 5.2.1 --- Float Class --- p.29 / Chapter 5.2.2 --- Optimization --- p.31 / Chapter 5.3 --- Digital Sine-Cosine Generator --- p.33 / Chapter 5.4 --- VHDL Floating Point operator generator --- p.35 / Chapter 5.4.1 --- Floating Point Multiplier Module --- p.35 / Chapter 5.4.2 --- Floating Point Adder Module --- p.36 / Chapter 5.5 --- Application to Solving Differential Equations --- p.38 / Chapter 5.6 --- Summary --- p.40 / Chapter 6 --- Function Approximation using Lookup Table --- p.42 / Chapter 6.1 --- Table Lookup Approximations --- p.42 / Chapter 6.1.1 --- Taylor Expansion --- p.42 / Chapter 6.1.2 --- Symmetric Bipartite Table Method (SBTM) --- p.43 / Chapter 6.1.3 --- Symmetric Table Addition Method (STAM) --- p.45 / Chapter 6.1.4 --- Input Range Scaling --- p.46 / Chapter 6.2 --- VHDL Extension --- p.47 / Chapter 6.3 --- Floating Point Extension --- p.49 / Chapter 6.4 --- The N-body Problem --- p.52 / Chapter 6.5 --- Implementation --- p.54 / Chapter 6.6 --- Summary --- p.56 / Chapter 7 --- Results --- p.58 / Chapter 7.1 --- Introduction --- p.58 / Chapter 7.2 --- GCD coprocessor --- p.58 / Chapter 7.3 --- Floating Point Module Library --- p.59 / Chapter 7.4 --- Digital sine-cosine generator (DSCG) --- p.60 / Chapter 7.5 --- Optimization --- p.62 / Chapter 7.6 --- Ordinary Differential Equation (ODE) --- p.63 / Chapter 7.7 --- N Body Problem Simulation (Nbody) --- p.63 / Chapter 7.8 --- Summary --- p.64 / Chapter 8 --- Conclusion --- p.66 / Chapter 8.1 --- Future Work --- p.68 / Chapter A --- Fly Formal Grammar --- p.70 / Chapter B --- Original Fly Source Code --- p.71 / Bibliography --- p.74

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Lo, Kwun Kit. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references (leaves 153-161). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Existing Approaches in Program Understanding --- p.2 / Chapter 1.1.1 --- Localized Program Understanding --- p.2 / Chapter 1.1.2 --- Whole System Analysis --- p.3 / Chapter 1.2 --- Example of Function Execution Probability Reduction of the Call Graph --- p.5 / Chapter 1.3 --- Organization of the Dissertation --- p.7 / Chapter 2 --- Preliminary Study --- p.8 / Chapter 2.1 --- Participants --- p.8 / Chapter 2.2 --- Study Design --- p.8 / Chapter 2.3 --- ispell --- p.10 / Chapter 2.3.1 --- Subject I1 (ispell) --- p.10 / Chapter 2.3.2 --- Subject PG1 (ispell) --- p.12 / Chapter 2.3.3 --- Subject PG2 (ispell) --- p.13 / Chapter 2.3.4 --- Subject I2 (ispell) --- p.14 / Chapter 2.3.5 --- ispell Analysis --- p.15 / Chapter 2.4 --- FreeBSD Kernel Malloc --- p.15 / Chapter 2.4.1 --- Subject I1 (FreeBSD) --- p.16 / Chapter 2.4.2 --- Subject PG1 (FreeBSD) --- p.17 / Chapter 2.4.3 --- Subject PG2 (FreeBSD) --- p.18 / Chapter 2.4.4 --- Subject I2 (FreeBSD) --- p.20 / Chapter 2.4.5 --- FreeBSD Analysis --- p.20 / Chapter 2.5 --- Threats to Validity --- p.21 / Chapter 2.6 --- Summary --- p.22 / Chapter 3 --- Approach --- p.24 / Chapter 3.1 --- Building Branch-Preserving Call Graphs --- p.26 / Chapter 3.1.1 --- Branch Reserving Call Graphs --- p.26 / Chapter 3.1.2 --- Branch-Preserving Call Graphs --- p.28 / Chapter 3.1.3 --- Example of BPCG Building Process --- p.31 / Chapter 3.2 --- System Function Removal --- p.34 / Chapter 3.3 --- Function Rating Calculation --- p.35 / Chapter 3.3.1 --- Rating Algorithm Complexity --- p.38 / Chapter 3.4 --- Building the Colored Call Graph --- p.39 / Chapter 3.5 --- Call Graph Reduction --- p.39 / Chapter 3.5.1 --- Remove-high-fan-in-functions Approach (FEPR-fanin) --- p.39 / Chapter 3.5.2 --- Remove-leaf-nodes Approach (FEPR-leaf) --- p.41 / Chapter 4 --- Validation --- p.42 / Chapter 4.1 --- Measures --- p.43 / Chapter 4.1.1 --- Inclusion Accuracy (IA) --- p.43 / Chapter 4.1.2 --- Reduction Efficiency (RE) --- p.44 / Chapter 4.1.3 --- Stability (S) --- p.45 / Chapter 4.2 --- Analysis of FEPR Techniques --- p.45 / Chapter 4.2.1 --- Settings --- p.45 / Chapter 4.2.2 --- Inclusion Accuracy (IA): --- p.47 / Chapter 4.2.3 --- Reduction Efficiency (RE): --- p.47 / Chapter 4.2.4 --- Stability (S) --- p.48 / Chapter 4.3 --- Ying and Tarr´ةs Approach --- p.48 / Chapter 4.3.1 --- Settings --- p.50 / Chapter 4.3.2 --- Inclusion Accuracy (IA) --- p.50 / Chapter 4.3.3 --- Reduction Efficiency (RE) --- p.51 / Chapter 4.3.4 --- Stability (S) --- p.51 / Chapter 4.4 --- Centrality Measure Approach --- p.52 / Chapter 4.4.1 --- Inclusion Accuracy (IA) --- p.53 / Chapter 4.5 --- Top-down Search Approach --- p.56 / Chapter 4.5.1 --- Reduction Efficiency (RE) --- p.57 / Chapter 4.6 --- Synthesized Analysis --- p.58 / Chapter 4.6.1 --- Inclusion Accuracy (IA) --- p.58 / Chapter 4.6.2 --- Reduction Efficiency (RE) --- p.59 / Chapter 4.6.3 --- Stability (S) --- p.59 / Chapter 4.6.4 --- Threats to Validity --- p.59 / Chapter 4.7 --- Summary --- p.60 / Chapter 5 --- Discussion --- p.62 / Chapter 5.1 --- Flexibility of Analysis --- p.62 / Chapter 5.2 --- "Existence of Function Pointers, GOTOs and Early Exits" --- p.62 / Chapter 5.3 --- Precision of Branch-Preserving Call Graphs --- p.63 / Chapter 5.4 --- Function Ranking and Recommender System --- p.64 / Chapter 5.5 --- Extending the Approach Beyond C --- p.66 / Chapter 6 --- Related Work --- p.67 / Chapter 6.1 --- Existing Approaches in Program Understanding --- p.67 / Chapter 6.1.1 --- Localized Program Understanding --- p.67 / Chapter 6.1.2 --- Whole Program Analysis --- p.69 / Chapter 6.2 --- Branch Prediction and Static Profiling --- p.73 / Chapter 7 --- Conclusions --- p.76 / Chapter A --- Call Graphs in Case Studies --- p.78 / Chapter B --- Source Files for BPCG Builder --- p.85 / Bibliography --- p.153

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Thesis (M.S.)--Oregon Graduate Center, 1983.

Thesis (Ph.D.)--University of Texas at Arlington, 2009.

Thesis (Ph. D.)--Lehigh University, 2001. / Includes vita. Includes bibliographical references (leaves 127-129).

Thesis (M.S. in Systems Engineering (Electronic Warfare))--Naval Postgraduate School, September 1990. / Thesis Advisor(s): Hershey, Scott. Second Reader: Sternberg, Joseph. "September 1990." Description based on title screen viewed on December 16, 2009. DTIC Descriptor(s): Electronic warfare, libraries, navy, computer programming, airborne warning and control system, receivers, radar receivers, flow charting, brazil, threats, air force, theses. DTIC Identifier(s): Systems approach, electronic warfare, Brazilian Air Force, military forces(foreign). Author(s) subject terms: Radar warming receivers, user data file reprogramming process. Includes bibliographical references (p. 61). Also available in print.

Dynamic optimizers for object-oriented languages collect a variety of profile data to drive optimization decisions. In particular, the dynamic call graph (DCG) informs key structural optimizations such as which methods to optimize and how to optimize them. Unfortunately, current low-overhead call-stack hardware and software sampling methods are subject to sampling bias, which loses accuracy of 40 to 50% when compared with a perfect call graph. This paper introduces DCG correction, a novel approach that uses static and dynamic control-flow graphs (CFGs) to improve DCG accuracy. We introduce the static frequency dominator (FDOM) relation, which extends the dominator relation on the CFG to capture relative execution frequencies and expose static constraints on DCG edges, which we use to correct DCG edge frequencies. Using conservation of flow principles, we further show how to use dynamic CFG basic block profiles to correct DCG edge frequencies intraprocedurally and interprocedurally. We implement and evaluate DCG correction in Jikes RVM on the SPEC JVM98 and DaCapo benchmarks. Default DCG sampling attains an average accuracy of 52-59% compared with perfect, whereas FDOM correction improves average accuracy to 64-68%, while adding 0.2% average overhead. The dynamic correction raises accuracy to 85% on average, while adding 1.2% average overhead. We then provide dynamically corrected DCGs to the inliner with mixed results -1% average degradations and improvements across a variety of configurations. However, prior work shows that increased DCG accuracy in production VMs has benefits. We believe that high-accuracy DCGs will become more important in the future as the complexity and modularity of object-oriented programs increases.

No description available.