Liu Chung Yan. / Thesis submitted in: September 2006. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 70-74). / Abstracts in English and Chinese. / ABSTRACT --- p.i / ACKNOWLEDGEMENTS --- p.v / TABLE OF CONTENTS --- p.vi / LIST OF FIGURES --- p.viii / Chapter CHAPTER 1. --- INTRODUCTION --- p.1 / Chapter 1.1 --- Woven Label --- p.3 / Chapter 1.2 --- Literature Review --- p.5 / Chapter 1.3 --- Objectives of the Research --- p.7 / Chapter CHAPTER 2. --- EXPERT LABEL PATTERN DESIGN SYSTEM --- p.10 / Chapter 2.1 --- Frame Based Expert System --- p.10 / Chapter 2.2 --- How the System Modify the Label --- p.13 / Chapter 2.3 --- System Operation --- p.15 / Chapter 2.4 --- Software Development - VLabel --- p.16 / Chapter 2.4.1 --- Color Settings for the System --- p.17 / Chapter 2.4.2 --- Generation of Label Template --- p.18 / Chapter 2.4.3 --- Creating New Label from Label Template --- p.20 / Chapter 2.4.4 --- Other Editing Tools --- p.22 / Chapter 2.4.5 --- Font and Edge Library --- p.23 / Chapter 2.5 --- Application Examples of the VLabel software --- p.24 / Chapter CHAPTER 3. --- VIRTUAL LABEL SIMULATION --- p.28 / Chapter 3.1 --- Geometric Modeling of the Label --- p.29 / Chapter 3.1.1 --- Geometric Modeling of Fabric Structure --- p.29 / Chapter 3.1.2 --- Generation of the Geometric Model of the Label --- p.39 / Chapter 3.2 --- Deformation of the Label under the Deformation of Warp Yarns --- p.45 / Chapter 3.2.1 --- Model of a Woven Cell --- p.45 / Chapter 3.2.2 --- Analysis of the Stretched Warp Threads during the Weaving Process … --- p.50 / Chapter 3.2.3 --- Analysis of the Warp Threads during the Relaxing Process --- p.51 / Chapter 3.3 --- Result of the Virtual Label Simulation --- p.52 / Chapter CHAPTER 4 --- CONCLUSIONS --- p.62 / APPENDIX I. DEFINITION OF CLASSES IN EXPERT SYSTEM --- p.63 / APPENDIX II.PUBLICATION LIST --- p.69 / BIBLIOGRAPHY --- p.70

Wu Yiu-Bun. / Thesis submitted in: September 2004. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 122-123). / Abstracts in English and Chinese. / Chapter Chapter 1. --- Introduction --- p.1 / Chapter Chapter 2. --- Previous Works --- p.2 / Chapter 2.1. --- Surface Patch Approach / Chapter 2.2. --- Triangular Facet Approach / Chapter Chapter 3. --- The Decomposition Algorithm --- p.7 / Chapter 3.1. --- Input to the Algorithm / Chapter 3.2. --- Overview of the Algorithm / Chapter 3.2.1. --- Voronoi Diagram Development / Chapter 3.2.2. --- Feature Point Determination / Chapter 3.2.3. --- Correspondence Establishment / Chapter 3.2.4. --- Surface Approximation / Chapter 3.3. --- Output of the Algorithm / Chapter Chapter 4. --- Voronoi Diagram Development --- p.16 / Chapter 4.1. --- Triangulation of the Parametric Space / Chapter 4.1.1. --- Degree of Triangulation / Chapter 4.2. --- Locating Bisectors / Chapter 4.2.1. --- Bisector Centroids / Chapter 4.2.2. --- Sub-triangulation / Chapter 4.3. --- Finalizing Bisectors / Chapter Chapter 5. --- Feature Point Determination --- p.31 / Chapter 5.1. --- Definition of Feature Points / Chapter 5.1.1. --- Continuous Sharp Turns / Chapter 5.1.2. --- Discrete Sharp Turns / Chapter 5.2. --- Parametric Coordinates of Feature Points / Chapter Chapter 6. --- Vertices Correspondence Attachment --- p.42 / Chapter 6.1. --- Validity of Correspondences / Chapter 6.2. --- Shape Normalization / Chapter 6.2.1. --- Normalization with Relative Position / Chapter 6.3. --- Ranking Process / Chapter 6.3.1. --- Forward and Backward Attachment / Chapter 6.3.2. --- Singly Linked Bisector Vertices / Chapter Chapter 7. --- Surface Fitting --- p.58 / Chapter 7.1. --- Parametric Patches / Chapter 7.1.1. --- Definition of Parametric Patch Region / Chapter 7.1.2. --- Local Parametric Coordinate System / Chapter 7.2. --- Parametric Grids / Chapter 7.2.1. --- Sample Points on the Patch Boundary / Chapter 7.2.2. --- Grid Generation / Chapter 7.3. --- Surface Patches Construction / Chapter 7.3.1. --- Knot Vectors / Chapter 7.3.2. --- Control Vertices / Chapter Chapter 8. --- Worked Example --- p.71 / Chapter 8.1. --- Example 1: Deformed Plane 1 / Chapter 8.2. --- Example 2: Deformed Plane 2 / Chapter 8.3. --- Example 3: Sphere / Chapter 8.4. --- Example 4: Hemisphere 1 / Chapter 8.5. --- Example 5: Hemisphere 2 / Chapter 8.6. --- Example 6: Shoe / Chapter 8.7. --- Example 7: Shark Main Body / Chapter 8.8. --- Example 8: Mask 1 / Chapter 8.9. --- Example 9: Mask 2 / Chapter 8.10. --- Example 10: Toy Car / Chapter Chapter 9. --- Result and Analysis --- p.101 / Chapter 9.1. --- Continuity between Patches / Chapter 9.2. --- Special Cases --- p.102 / Chapter 9.2.1. --- Degenerated Patch / Chapter 9.2.2. --- S-Shaped Feature / Chapter 9.3. --- Comparison --- p.105 / Chapter 9.3.1. --- Example 1: Deformed Plane 1 / Chapter 9.3.2. --- Example 2: Deformed Plane 2 / Chapter 9.3.3. --- Example 3: Sphere / Chapter 9.3.4. --- Example 4: Hemisphere 1 / Chapter 9.3.5. --- Example 5: Hemisphere 2 / Chapter 9.3.6. --- Example 6: Shoe / Chapter 9.3.7. --- Example 7: Shark Main Body / Chapter 9.3.8. --- Example 8: Mask 1 / Chapter 9.3.9. --- Example 9: Mask 2 / Chapter 9.3.10. --- Example 10: Toy Car / Chapter Chapter 10. --- Conclusion --- p.119 / References --- p.122

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Relational database systems have successfully solved many business data processing problems. The primary reason of this success is that the relational data model provides a simple, yet flexible view of data as tables. In studying VLSI/CAD data, we noticed that they are often represented in formats similar to relational tuples. Therefore, they can be stored easily in relational tables. However, it is generally agreed that conventional relational database systems are inefficient for VLSI/CAD applications, since such applications often access large amounts of data repetitively. In order to solve this problem, we designed and implemented a data mapping subsystem that converts VLSI/CAD data stored in relational tables into internal data structures so that they can be efficiently manipulated in C. By using our data mapping language, we could reduce the amount of code required by the data-structure construction parts of some real VLSI/ CAD tools to about 1/10 of that required by C implementation. Our data-structure builder consumes several times more CPU cycles. / Graduation date: 1991

In the era of system-on-chip, many hardware modules are embedded on a single chip. More messages communicated among on-chip modules. On-chip communication bandwidth is thus scaled up dramatically. It causes significant increase of routing area as well as relative reduction of system performance. It affects overall feasibility of a system chip. In order to solve the problem and meet the communication performance requirement of application systems. We need to consider factors that affect overall system performance and cost, communication resource allocation, message routing, and transmission control design. Thus, we proposed a soft real-time communication synthesis method. It applied the simulated annealing optimization method.. In the process, it carries out several tasks: calibration of dynamic communication cases, communication resource allocation, message routing path generation, and estimation of overall communication performance and system cost. In this research, we designed the experimental software of the communication synthesis method. We will perform experiments for its system evaluation to verify its effectiveness on system-on-chip designs.

Thesis (Ph.D.)--Virginia Commonwealth University, 2009. / Prepared for: Dept. of Medicinal Chemistry. Title from title-page of electronic thesis. Bibliography: leaves 169-185.

Thesis (M.S.)--Brigham Young University. Dept. of Mechanical Engineering, 2008. / Includes bibliographical references (p. 103-104).

Thesis (M.S.)--Brigham Young University. Dept. of Mechanical Engineering, 2008. / Includes bibliographical references (p. 97-98).

Thesis (M.S.)--Rochester Institute of Technology, 2010. / Typescript. Includes bibliographical references (leaves 94-99).