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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

CAD algorithms for VLSI design and manufacturing

Huang, Li-da, Wong, D. F., Mok, Aloysius Ka-Lau, January 2003 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2003. / Supervisors: Martin D.F. Wong and Aloysius K. Mok. Vita. Includes bibliographical references. Available also from UMI Company.
2

Topological data structure and algorithms for cell-complex based non-manifold form feature modeling /

Lam, Tak-wah. January 1994 (has links)
Thesis (M. Phil.)--University of Hong Kong, 1995. / Includes bibliographical references (leaves 120-126).
3

CAD algorithms for field programmable logic devices /

Lee, Kok Kiong, January 2000 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 134-144). Available also in a digital version from Dissertation Abstracts.
4

Graphics Processing Unit-Based Computer-Aided Design Algorithms for Electronic Design Automation

Han, Yiding 01 May 2014 (has links)
The electronic design automation (EDA) tools are a specific set of software that play important roles in modern integrated circuit (IC) design. These software automate the design processes of IC with various stages. Among these stages, two important EDA design tools are the focus of this research: floorplanning and global routing. Specifically, the goal of this study is to parallelize these two tools such that their execution time can be significantly shortened on modern multi-core and graphics processing unit (GPU) architectures. The GPU hardware is a massively parallel architecture, enabling thousands of independent threads to execute concurrently. Although a small set of EDA tools can benefit from using GPU to accelerate their speed, most algorithms in this field are designed with the single-core paradigm in mind. The floorplanning and global routing algorithms are among the latter, and difficult to render any speedup on the GPU due to their inherent sequential nature. This work parallelizes the floorplanning and global routing algorithm through a novel approach and results in significant speedups for both tools implemented on the GPU hardware. Specifically, with a complete overhaul of solution space and design space exploration, a GPU-based floorplanning algorithm is able to render 4-166X speedup, while achieving similar or improved solutions compared with the sequential algorithm. The GPU-based global routing algorithm is shown to achieve significant speedup against existing state-of-the-art routers, while delivering competitive solution quality. Importantly, this parallel model for global routing renders a stable solution that is independent from the level of parallelism. In summary, this research has shown that through a design paradigm overhaul, sequential algorithms can also benefit from the massively parallel architecture. The findings of this study have a positive impact on the efficiency and design quality of modern EDA design flow.

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