Due to the rapid advancement of VLSI technology, functions of multimedia systems (e.g. MP3, image processing etc,) become more complex nowadays. Therefore, more complicated system architecture and powerful computing ability are required to attain real-time process. In order to fulfill the requirement of cost and efficiency, multimedia systems usually consist of processors, ASICs and other various components. Diverse real-time functions of multimedia system can be implemented via co-operation of these components. However, these components have the differences in area, efficiency, and cost. Accordingly, it is necessary to establish a useful method and tool to decide better system architecture. ¡@¡@The main objective of the thesis is to develop a decision tool of system architecture. Given the system specification and constraints of a multimedia system, it can quickly decide a good system architecture to satisfy the constraints in accordance with the system specification . Except for partitioning various functions and mapping functions to hardware components, the decision tool must implement scheduling and pipelining to fulfill resource constraints and reach the real-time requirement. A great deal of time and cost for implementing the multimedia system can be reduced by careful scheduling and pipelining. Besides, owing to the pressure of time to market in system development, we propose a series of design flow to speed up the design process. All decision tasks in the flow are finished by automatic or semi-automatic method to reduce the exhaustion of manpower and time. Finally, we make experiments with the proposed tool on several multimedia systems. The results show that the automatic process can conform to constraints which set up by system specifications and ensure the accuracy of the process.

Security assurance in a computer system can be viewed as distinguishing between self and non-self. Artificial Immune Systems (AIS) are a class of machine learning (ML) techniques inspired by the behavior of innate biological immune systems, which have evolved to accurately classify self-behavior from non-self-behavior. This work aims to leverage AIS-based ML techniques for identifying certain behavioral traits in high level hardware descriptions, including unsafe or undesirable behaviors, whether such behavior exists due to human error during development or due to intentional, malicious circuit modifications, known as hardware Trojans, without the need fora golden reference model. We explore the use of Negative Selection and Clonal Selection Algorithms, which have historically been applied to malware detection on software binaries, to detect potentially unsafe or malicious behavior in hardware. We present a software tool which analyzes Trojan-inserted benchmarks, extracts their control and data-flow graphs (CDFGs), and uses this to train an AIS behavior model, against which new hardware descriptions may be tested.

This dissertation addresses the confidentiality aspect of the information security problem from the viewpoint of the software architecture. It presents a new approach to secure system design in which the desired security properties, in particular, confidentiality, of the system are proven to hold at the architectural level. The architecture description language Wright is extended so that confidentiality authorizations can be specified. An architectural description in Wright/c, the extended language, assigns clearance to the ports of the components and treats security labels as a part of data type information. The security labels are declared along with clearance assignments in an access control lattice model, also expressed in Wright/c. This enables the static analysis of data flow over the architecture subject to confidentiality requirements as per Bell-LaPadula principles. An algorithm takes the Wright/c description and the lattice model as inputs, and checks if there is a potential violation of the Bell-LaPadula principles. The algorithm also detects excess privileges. A software tool, which features an XML-based front-end to the algorithm is constructed. Finally, the algorithm is analyzed for its soundness, completeness and computational complexity.

The design of a common architecture that can support multiple data-flow patterns (or contexts) embedded in complex control flow structures, in applications like multimedia processing, is particularly challenging when the target platform is a Field Programmable Gate Array (FPGA) with a heterogeneous mixture of device primitives. This thesis presents scheduling and mapping algorithms that use a novel area cost metric to generate resource aware context adaptable architectures. Results of a rigorous analysis of the methodology on multiple test cases are presented. Results are compared against published techniques and show an area savings and execution time savings of 46% each.