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This thesis describes discrete robust adaptive control methods based on using slow sampling and slow adaptation. For the stability analysis, we consider that the plant model order is not exactly known and assume that the estimation model order is lower than the plant model order. A stability condition is derived with a given upper limit for the adaptation gain which is related to a strictly positive real operator. Discussion of the relation between sampling and stability condition is then given. For the robust adaptive control design, we study slow adaptation and predictive control. For the slow adaptation, the main idea is to use only good estimates and use a compensation filter. Some frequency domain information on the plant is necessary for this method. For predictive control, we discuss the relationship between the extended control horizon and the critical sampling. For a simple case, it is shown that the larger extended control horizon brings more robust adaptive control. The purpose of this thesis is to provide robust discrete adaptive controller design guidelines, especially in such cases as using slow sampling frequency, slow adaptation rate. It is true that in practice, for various discrete adaptive control algorithms, slow sampling and slow adaptation rate will bring more robustness. The use of slow sampling and slow adaptation rate is simple and economic, thus a careful choice of sampling rate and adaptation rate is highly recommended. This thesis provides such guidelines for choosing proper sampling rate and adaptation rate for robust discrete adaptive control. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

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Reliable controller designs have been developed in this thesis for a number of finite-horizon and infinite-horizon problems with possibly non-zero initial conditions. These reliable controllers assure that system stability and system performance will be maintained despite certain system faults. The performance measure used in this thesis is an "H[subscript ���]-like norm", which is an induced two-norm from all exogenous signals and initial conditions to the regulated output and final states. Controller designs and existence conditions are presented for a reliable controller for faults in any pre-selected subset of actuators or sensors. Also, controller designs and an existence condition are presented for a reliable controller for any single sensor or actuator fault using sensor and actuator redundancy. / Graduation date: 1999

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published_or_final_version / abstract / Industrial and Manufacturing Systems Engineering / Doctoral / Doctor of Philosophy

Multi-level decision feedback equalization (MDFE) is an effective technique to remove inter-symbol interference (ISI) from disk readback signals, which uses the simple architecture of decision feedback equalization. Parallelism which doubles the symbol rate can be realized by setting the first tap of the feedback filter to zero. A mixed-signal implementation has been chosen for the parallel MDFE, in which coefficients for the 9-tap feedback filter are adapted in the digital domain by 10-bit up/ down counters; 6-bit current mode D/A converters are used to convert digital coefficients to differential current signals which are summed with the forward equalizer (FE) output, and a flash A/D is used to make decisions and generate error signals for adaptation. In this thesis, a description of the parallel structure and the adaptation algorithm are presented with behavioral level verification. The circuit design and layout were carried out in HP 1.2um n-well CMOS process. The design of the high-speed counter and the current-mode D/A are discussed. HSPICE simulations show that a symbol rate of 100Mb/s for the feedback equalizer is readily achieved. / Graduation date: 1997

Decision feedback equalizer (DFE) is an effective method to remove inter-symbol interference (ISI) from a disk-drive read channel. Analog IC implementations of DFE potentially offers higher speed, smaller die area, and lower power consumption when compared to their digital counterparts. Most of the available DFE equalizers were realized by using digital FIR filters preceded by a flash A/D converter. Both the FIR filter and flash A/D converter are the major contributers to the power dissipation. However, this project focuses on the analog IC implementations of the DFE to achieve high speed and low power consumption. In other words, this project gets intensively involved in the design of a large-input highly-linear voltage-to-current converter, the design of a high-speed low-power 6-bit comparator, and the design of a high-speed low-power 6-bit current-steering D/A converter. The design and layout for the proposed analog equalizer are carried out in a 1.2 pm n-well CMOS process. HSPICE simulations show that an analog DFE with 100 MHz clock frequency and 6-bit accuracy can be easily achieved. The power consumption for all the analog circuits is only about 24mW operating under a single 5V power supply. / Graduation date: 1997