In this thesis, we take an application of multiple symbol differential detection (MSDD) technique in direct-sequence code division multiple access (CDMA) system. It is well- known that MSDD is an effective noncoherent demodulator which outperform the conventional M-ary differential phase shift keying (MDPSK) in additive white Gaussian noise (AWGN) channel. Take MPSK demodulator into consideration, the performance of MSDD based on noncoherent demodulation approaches the performance of coherent demodulation. However, there is little research about MSDD in frequency-selective fading channel. We are now combining the MSDD and Rake receiver to be the signal demodulator. In conventional, there are two kinds of Rake receivers. One is coherent demodulator. Another is noncoherent demodulator. For coherent demodulation, it needs to have channel estimation at each path. The advantage is that the performance will be improved. On the other hand, the disadvantage is complexity and operation will increase. On the contrast, for noncoherent demodulation, it is the performance degradation and complexity simplification. In this thesis, We suggest a multiple symbol differential detection on Rake receiver for CDMA system. From our computer simulation, only for hard decision, the performance is improved and the improvement is proportional to the number of multipath and the number of the length of multiple symbol. This will not happen in conventional MDPSK. However, from our observation, the improvement of performance is degrading as the number of multipath increase. Thus, we employee the technique of Viterbi decoding differential detection (VDDD) to demodulate the differential sequence. By the property of decision interval, the VDDD can obtain additional improvement.

In this thesis, the VLSI implementation of Viterbi decoder using a design and simulation platform called SystemC is studied. For this purpose, the architecture of Viterbi decoder is tried to be optimized for VLSI implementations. Consequently, two novel area efficient structures for reconfigurable Viterbi decoders have been suggested. The traditional and SystemC design cycles are compared to show the advantages of SystemC, and the C++ platforms supporting SystemC are listed, installation issues and examples are discussed. The Viterbi decoder is widely used to estimate the message encoded by Convolutional encoder. For the implementations in the literature, it can be found that special structures called trellis have been formed to decrease the complexity and the area. In this thesis, two new area efficient reconfigurable Viterbi decoder approaches are suggested depending on the rearrangement of the states of the trellis structures to eliminate the switching and memory addressing complexity. The first suggested architecture based on reconfigurable Viterbi decoder reduces switching and memory addressing complexity. In the architectures, the states are reorganized and the trellis structures are realized by the usage of the same structures in subsequent instances. As the result, the area is minimized and power consumption is reduced. Since the addressing complexity is reduced, the speed is expected to increase. The second area efficient Viterbi decoder is an improved version of the first one and has the ability to configure the parameters of constraint length, code rate, transition probabilities, trace-back depth and generator polynomials.