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Thesis (M.S.)--University of Wisconsin--Madison, 1966. / eContent provider-neutral record in process. Description based on print version record. Bibliography: l. 93-94.

The use of expensive and highly specialized equipment in any industry is only advisable if the eost of the equipment can be justified by a sufficiently large output. The greater the output, the smaller will be the cost of the equipment to be borne by each unit. Thus, once such equipment has been purchased, management endeavours to maintain output at a maximum in order to reduce unit costs or to increase profits. It is for this reason that airline managements continually endeavour to increase the utilization of jet aircraft. By increasing the number of revenue flying hours only one hour each week on one jet aircraft, an airline will realize an additional net contribution to overhead (or profits) of approximately $60,000 per year. One method of increasing utilization is to decrease the downtime of the aircraft for maintenance purposes. This requires a reduction of the total elapsed time of the maintenance check. The critical path technique has found wide application in solving the general problem of reducing the time required to complete a project which consists of many inter-related jobs. For example, the technique has been used to reduce the time required for constructing a building, for completing the periodic overhaul of a chemical plant, and for completing the Polaris Missile Development Program. It was therefore felt that the critical path technique might be of use in solving this problem of increasing the utilization of jet aircraft. This thesis, based on the results of a study carried out at Canadian Pacific Air Lines during the months of May through August, 1963, describes the various ways in which the technique can be of use in solving this problem. It was found that the technique did have a wide applicability. In the initial period of application, it would be of great value as a tool for analyzing the problems of the check. It can be used both to point out the jobs or chains of jobs which prohibit the reduction of the check time and also to direct the revision of the scheduling of these jobs in such a way that the elapsed time is reduced. This reduction of elapsed time will have the effect of increasing the number of jobs which must be completed at the earliest possible time if the check completion time is to be a minimum. As a result there will be a greater need to use the technique both for scheduling and monitoring all the jobs of the check. / Business, Sauder School of / Graduate

Conventional logic circuit designs are based on fully complementary CMOS logic circuits. In the past decade, many Pass-Transistor Logic (PTL) circuits have been proposed that are claimed to have better performance in area, speed and power. Most current PTL logic circuits are composed of a limited number of basic PTL cells (say 2 to 5 types of cells only). However, current placement-and-routing (P&R) CAD tools are mainly designed based on CMOS cell library which usually contains many cells with different logic functions. Thus the P&R tool does not fully exploit the features of the synthesized PTL gate-level netlists. In this thesis, we present a P&R tool dedicated to the generation of the final physical layout for the PTL netlists that are generated from a PTL synthesizer. This backend tool considers the efficient placement and routing of the PTL cells in order to reduce the area cost and to reduce the impact of the interconnection wirings on speed and power performances. Besides, in this thesis, the critical paths of the PTL netlists will be identified and the corresponding input patterns to activate these critical paths will be generated for post-layout speed simulation using HSPICE or Nanosim. In summary, the layout generator in this thesis performs the P&R of PTL netlists and also automatically find the critical paths and their corresponding input patterns.

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