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Project managers today rely on scheduling tools based on the Critical Path Method (CPM) to determine the overall project duration and the activities’ float times. Such data provide important information about the degree of flexibility with respect to the project schedule as well as the critical and noncritical activities, which leads to greater efficiency in planning and control of projects. While CPM has been useful for scheduling construction projects, years of practice and research have highlighted a number of serious drawbacks that limit its use as a decision support tool. The traditional representation of CPM lacks the ability to clearly record and represent detailed as-built information such as slow/fast progress and complete representation of work interruptions caused by the various parties involved. In addition, CPM is based on two unrealistic assumptions: that the project deadline is not restricted and that resources are unlimited. With CPM, therefore, the most cost-effective corrective actions needed in order to recover delays and overruns cannot be determined. This research is based on the view that many of the drawbacks of CPM stem from the rough level of detail at which progress data is represented and analyzed, where activities’ durations are considered as continuous blocks of time. To overcome CPM drawbacks, this research presents a new Critical Path Segments (CPS) mechanism, with its mathematical formulation, that offers a finer level of granularity by decomposing the duration of each activity into separate time segments. The CPS mechanism addresses the problems with CPM in three innovative ways: (1) the duration of an activity is represented as a series of separate time segments; (2) the representation of the progress of an activity is enhanced; and (3) an optimization mechanism to incorporate project constraints into the CPS analysis. To demonstrate the ability of the CPS to provide better analysis than the traditional CPM, a number of case studies are used to show its ability to (1) simplify network relationships and accurately calculate floats and critical path(s); (2) achieve better resource allocation and facilitate accurate delay analysis; and (3) overcome problems associated with the use of multiple resource calendars. This research represents a change from well-known CPM techniques and has the potential to revolutionize and simplify the analysis of ongoing and as-built schedules. The developed CPS technique is expected to help project managers achieve a better level of control over projects and their corrective actions because it offers better visualization, optimization, and decision support for meeting project goals within the specified constraints.

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Thesis (M.Eng.) -- Memorial University of Newfoundland. 1975. / Typescript. Bibliography : leaves 102-103. Also available online.

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The Dynamic Voltage Scaling (DVS) technique has proven to be ideal in regard to balancing performance and energy consumption of a processor since it allows for almost cubic reduction in dynamic power consumption with only a nearly linear reduction in performance. Due to its virtue, the DVS technique has been used for the two main purposes: energy-saving and temperature reduction. However, recently, a Dynamic Voltage Scaled (DVS) processor has lost its appeal as process technology advances due to the increasing Process, Voltage and Temperature (PVT) variations. In order to make a processor tolerant to the increasing uncertainties caused by such variations, processor designers have used more timing margins. Therefore, in a modern-day DVS processor, reducing voltage requires comparatively more performance degradation when compared to its predecessors. For this reason, this technique has a lot of room for improvement for the following facts. (a) From an energy-saving viewpoint, excessive margins to account for the worst-case operating conditions in a DVS processor can be exploited because they are rarely used during run-time. (b) From a temperature reduction point of view, accurate prediction of the optimal performance point in a DVS processor can increase its performance. In this dissertation, we propose four performance improvement ideas from two different uses of the DVS technique. In regard to the DVS technique for energy-saving, in this dissertation, we introduce three different types of margin reduction (or margin decision) techniques. First, we introduce a new indirect Critical Path Monitor (CPM) to make a conventional DVS processor adaptive to its given environment. Our CPM is composed of several Slope Generators, each of which generates similar voltage scaling slopes to those of potential critical paths under a process corner. Each CPR in the Slope Generator tracks the delays of potential critical paths with minimum difference at any condition in a certain voltage range. The CPRs in the same Slope Generator are connected to a multiplexer and one of them is selected according to a current voltage level. Calibration steps are done by using conventional speed-binning process with clock duty-cycle modulation. Second, we propose a new direct CPM that is based on a non-speculative pre-sampling technique. A processor that is based on this technique predicts timing errors in the actual critical paths and undertakes preventive steps in order to avoid the timing errors in the event that the timing margins fall below a critical level. Unlike direct CPM that uses circuit-level speculative operation, although the shadow latch can have timing error, the main Flip-Flop (FF) of our direct CPM never fails, guaranteeing always-correct operation of the processor. Our non-speculative CPM is more suitable for high-performance processor designs than the speculative CPM in that it does not require original design modification and has lower power overhead. Third, we introduce a novel method that determines the most accurate margin that is based on the conventional binning process. By reusing the hold-scan FFs in a processor, we reduce design complexity, minimize hardware overhead and increase error detecting accuracy. Running workloads on the processor with Stop-Go clock gating allows us to find which paths have timing errors during the speed binning steps at various, fixed temperature levels. From this timing error information, we can determine the different maximum frequencies for diverse operating conditions. This method has high degree of accuracy without having a large overhead. In regard to the DVS technique for temperature reduction, we introduce a run-time temperature monitoring scheme that predicts the optimal performance point in a DVS processor with high accuracy. In order to increase the accuracy of the optimal performance point prediction, this technique monitors the thermal stress of a processor during run-time and uses several Look-Up Tables (LUTs) for different process corners. The monitoring is performed while applying Stop-Go clock gating, and the average EN value is calculated at the end of the monitoring time. Prediction of the optimal performance point is made using the average EN value and one of the LUTs that corresponds to the process corner under which the processor was manufactured. The simulation results show that we can achieve maximum processor performance while keeping the processor temperature within threshold temperature. / text

Thesis (PhD)--University of Stellenbosch, 2004. / ENGLISH ABSTRACT: Please refer to full text for abstract.

published_or_final_version / Business Administration / Master / Master of Business Administration

In the present work, stochastic network models representing a project as a set of activities are studied, as well as different approaches to these models. The critical path method, stochastic network models with probability constraints, finding a reference project duration, worst-case analysis in stochastic networks and optimization of the parameters of the probability distributions of the activity durations are studied. Use of stochastic network models in telecommunications networks is also briefly presented. In a numerical study, some of these models are implemented and the~related numerical results are analyzed.

With advances in technology, modern integrated circuits have higher complexities and reduced transistor sizing. In deep sub-micron, the parameter variation-control is difficult and component delays vary from one manufactured chip to another. Therefore, the delays are not discrete values but are a statistical quantity, and statistical evaluation methods have gained traction. Furthermore, fault injection based gate-level fault coverage is non-scalable and statistical estimation methods are preferred. This dissertation focuses on scalable statistical methods to select critical paths in the presence of process variations, and to improve the defect coverage for complex integrated circuits. In particular, we investigate the sensitization probability of a path by a test pattern under statistical delays. Next, we investigate test pattern generation for improving the sensitization probability of a path, selecting critical paths that yield high defect coverage, and scalable method to estimate fault coverage of complex designs using machine learning techniques.