This research focuses on developing a model to predict the yield of a printed circuit board manufactured on a given assembly line. Based on an extensive literature review as well as discussion with industrial partners, it was determined that there is no tool available for assisting engineers in determining reliable estimates of their production capabilities as they introduce new board designs onto their current production lines. Motivated by this need, a more in-depth study of manufacturing yield as well as the electronic assembly process was undertaken. The relevant literature research was divided into three main fields: process modeling, board design, and PCB testing. The model presented in this research combines elements from process modeling and board design into a single yield model. An optimization model was formulated to determine the fault probabilities that minimize the difference between actual yield values and predicted yield values. This model determines fault probabilities (per component type) based on past production yields for the different board designs assembled. These probabilities are then used to estimate the yields of future board designs. Two different yield models were tested and their assumptions regarding the nature of the faults were validated. The model that assumes independence between faults provided better yield predictions. A preliminary case study was performed to compare the performance of the presented model with that of previous models using data available from the literature. The proposed yield model predicts yield within 3% of the actual yield value, outperforming previous regression models that predicted yield within 10%, and artificial neural network models that predicted yield within 5%. A second case study was performed using data gathered from actual production lines. The proposed yield model continued to provide very good yield predictions. The average difference with respect to the actual yields from this case study ranged between 1.25% and 2.27% for the lines studied. Through sensitivity analysis, it was determined that certain component types have a considerably higher effect on yield than others. Once the proposed yield model is implemented, design suggestions can be made to account for manufacturability issues during the design process. / Master of Science

With advances in technology, modern integrated circuits have higher complexities and reduced transistor sizing. In deep sub-micron, the parameter variation-control is difficult and component delays vary from one manufactured chip to another. Therefore, the delays are not discrete values but are a statistical quantity, and statistical evaluation methods have gained traction. Furthermore, fault injection based gate-level fault coverage is non-scalable and statistical estimation methods are preferred. This dissertation focuses on scalable statistical methods to select critical paths in the presence of process variations, and to improve the defect coverage for complex integrated circuits. In particular, we investigate the sensitization probability of a path by a test pattern under statistical delays. Next, we investigate test pattern generation for improving the sensitization probability of a path, selecting critical paths that yield high defect coverage, and scalable method to estimate fault coverage of complex designs using machine learning techniques.

Traditional solutions for test and reliability do not scale well for modern designs with their size and complexity increasing with every technology generation. Therefore, in order to meet time-to-market requirements as well as acceptable product quality, it is imperative that new methodologies be developed for quickly evaluating a system in the presence of faults. In this research, statistical methods have been employed and implemented to 1) estimate the stuck-at fault coverage of a test sequence and evaluate the given test vector set without the need for complete fault simulation, and 2) analyze design vulnerabilities in the presence of radiation-based (soft) errors. Experimental results show that these statistical techniques can evaluate a system under test orders of magnitude faster than state-of-the-art methods with a small margin of error. In this dissertation, I have introduced novel methodologies that utilize the information from fault-free simulation and partial fault simulation to predict the fault coverage of a long sequence of test vectors for a design under test. These methodologies are practical for functional testing of complex designs under a long sequence of test vectors. Industry is currently seeking efficient solutions for this challenging problem. The last part of this dissertation discusses a statistical methodology for a detailed vulnerability analysis of systems under soft errors. This methodology works orders of magnitude faster than traditional fault injection. In addition, it is shown that the vulnerability factors calculated by this method are closer to complete fault injection (which is the ideal way of soft error vulnerability analysis), compared to statistical fault injection. Performing such a fast soft error vulnerability analysis is very cruicial for companies that design and build safety-critical systems. / text

With the increasing complexity of modern day processors and system-on-a-chip (SOCs), designers invest a lot of time and resources into testing and validating these designs. To reduce the time-to-market and cost, the techniques used to validate these designs have to constantly improve. Since most of the design activity has moved to the register transfer level (RTL), test methodologies at the RTL have been gaining momentum. We present a novel functional test generation framework for functional test generation at RTL. A popular software-based metric for measuring the effectiveness of an RTL test suite is branch coverage. But exercising hard-to-reach branches is still a challenge and requires good understanding of the design semantics. The proposed framework uses static analysis to extract certain semantics of the circuit and uses several data structures to model these semantics. Using these data structures, we assist the branch-guided search to exercise these hard-to-reach branches. Since the correlation between high branch coverage and detecting defects and bugs is not clear, we present a new metric at the RTL which augments the RTL branch coverage with state values. Vectors which have higher scores on the new metric achieve higher branch and state coverages, and therefore can be applied at different levels of abstraction such as post-silicon validation. Experimental results show that use of the new metric in our test generation framework can achieve a high level of branch and fault coverage for several benchmark circuits, while reducing the length of the vector sequence. This work was supported in part by the NSF grant 1016675. / Master of Science

This thesis deals with problematics of secure operations of microcontrollers. During long-term use, the microcontrollers can be affected by error or malfunction. The aim of this thesis is to describe the types of errors which can affect processors, cause of creation of these errors and possibilities of preventing malfunctions in microcontrollers. There is many problems connected with operation of microcontrollers, therefore there are many methods to prevent these problems. First part of this thesis deals with description of types of mistakes and with attempts of theirs modelling. Second part of this thesis narrate possibilities of preventing each type of mistake during designing the system or during operation of microcontroller and explaining methods of fault toleration by using redundant circuits in case of hardware fault and by modifying source code in case of software faults. In third part the hazard analytical methods are described. The recognition of events able to damage the system has high importance. The risk analysis takes place during developing and during operation of the system. Fourth part is trying to describe some of the processor testing techniques as main method of finding errors before operating use of microcontroller. Last part attempts to practical draft of testing algorithm for chosen microprocessor and application of one of analytical techniques.

This work deals with testability analysis of digital circuits and fault coverage. It contains a desription of digital systems, their diagnosis, a description of tools for generating and applying tests and sets of benchmark circuits. It describes the testing of circuits and experimentation in tool TASTE for testability analysis and commercial tool for generating and applying tests. The experiments are focused on increase the testability of circuits.

The criticality of the applications modeled by the real-time software places stringent requirements on software quality before deploying into real use. Though automated test tools can be used to run a large number of tests efficiently, the functionality of any test tool is not complege without providing a means for analyzing the test results to determine potential problem sub-domains and sub-domains that need to be covered, and estimating the reliability of the modeled system. This thesis outlines a solution strategy and implementation of that strategy for deriving quantitative metrics from domain testing of real-time control software tested via simulation. The key portion of this thesis addresses the combinatorial problems involved with effective evaluation of test coverage and provides the developer with reliability metrics from testing of the software to gain confidence in the test phase of development. The two approaches for reliability analysis- time domain and input domain approaches are studied and a hybrid approach that combines the strengths of both these approaches is proposed. A Reliability analysis Test Tool (RATT) has been developed to implement the proposed strategies. The results show that the metrics are practically feasible to compute and can be applied to most real-time software.

While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid <em>silicon diagnosis</em>. In this thesis, test point insertions are conducted with the aim to detect more faults and also synergistically distinguish currently indistinguishable fault-pairs. We achieve this by identifying those points in the circuit, which are not only hard-to-test but also lie on distinguishable frontiers, as Testability-Diagnosability (TD) points. To this end, we propose a novel low-cost metric to identify such TD points. Further, we propose a new DFT + DFD architecture, which adds just one pin (to identify test/functional mode) and small additional combinational logic to the circuit under test. Our experiments indicate that the proposed architecture can distinguish 4x more previously indistinguishable fault-pairs than existing DFT architectures while maintaining similar fault coverages. Further, the experiments illustrate that quality results can be achieved with an area overhead of around 5%. Additional experiments conducted on hard-to-test circuits show an increase in <em>fault coverage</em> by 48% while maintaining similar diagnostic resolution. Built-in Self Test (BIST) is a technique of adding additional blocks of hardware to the circuits to allow them to perform self-testing. This enables the circuits to test themselves thereby reducing the dependency on the expensive external automated test equipment (ATE). At the end of a test session, BIST generates a signature which is a compaction of the obtained output responses of the circuit for that session. Comparison of this signature with the reference signature categorizes the circuit as error free or buggy. While BIST provides a quick and low cost alternative to check circuit's correctness, diagnosis in BIST environment remains poor because of the limited information present in the lossily compacted final signature. The signature does not give any information about the possible defect location in the circuit. To facilitate diagnosis, researchers have proposed the use of two additional on-chip embedded memories,response memory to store reference responses and fail memory to store failing responses. We propose a novel architecture in which only one additional memory is required. Experimental results conducted on benchmark circuits substantiate that the same fault coverage can be maintained using just 5% of the available test vectors. This reduces the size of memory required to store responses which in turn reduces area overhead. Further, by adding test points to the circuit using our proposed architecture, we can improve the diagnostic resolution by 60% with respect to external testing. / Master of Science

Software Product Line Engineering (SPLE) is an approach used in the development of similar products, which explores the systematic reuse of software artifacts. The SPLE process has several activities executed to ensure software quality. Quality assurance is of vital importance for achieving and maintaining a high quality of all kinds of artifacts, such as products and processes. Testing activities are widely used in the industry for quality management. However, the effort for applying testing is usually high, and increasing the testing efficiency is a major concern of all systems engineering activities. A common means of increasing efficiency is automation of the test execution and the test design. Automated test design can be performed using approaches such as Model-Based Testing (MBT) in which the real behavior of a software system is compared to an abstract test model. Several techniques, processes, and strategies were developed for SPLE testing, but still many problems are open in this area of research. The challenge in focus is the reduction of the overall test effort required to test SPLE products. Test effort can be reduced by maximizing test reuse using models that take advantage of the similarity between products. The thesis goal is to automate the generation of small test-suites with high fault detection and low test redundancy between products. To achieve the goal, equivalent tests are identified for a set of products using complete and configurable test-suites. Two research directions are explored, one is product-based centered, and the other is product line-centered. For test design, test-suites that have full fault coverage were generated from state machines with and without feature constraints. A prototype implementation tool was developed for test design automation. In addition, the proposed approach was evaluated using examples, experimental studies, and an industrial case study for the automotive domain. The results indicates test effort reduction of 36% in the first research direction for a product line with 24 products, and in the second research direction increasing test effort reduction based on the number of products that require testing. For 6 products 15% reduction (from case study), and for 20 random products 50% reduction (from experimental studies). / Engenharia de Linha de Produto de Software (SPLE) é uma abordagem utilizada no desenvolvimento de produtos similares, que explora a reutilização sistemática de artefatos de software. O processo da SPLE executa várias atividades para garantir a qualidade do software. Atividades de garantia de qualidade são fundamentais para alcançar e manter altos níveis de qualidade em todos os tipos de artefatos de software, tais como produtos e processos. Atividades de teste são amplamente utilizadas na indústria para o gerenciamento de qualidade. No entanto, o esforço para a aplicação de testes geralmente é alto e melhorar a eficiência dos testes é um desafio relacionado a todas as atividades da engenharia de sistemas. Uma maneira de melhorar a eficiência da atividade de teste é automatizar a geração e execução dos testes. A geração automática de testes pode ser realizada por abordagens tais como o Teste Baseado em Modelos (TBM), em que o comportamento real do sistema de software é comparado a um modelo de teste abstrato. Várias técnicas, processos e estratégias foram desenvolvidas para o teste de SPLE, contudo, existem diversos desafios nessa área de pesquisa. O desafio em foco é a redução do esforço geral de teste necessário para testar produtos da SPLE. O esforço de teste pode ser reduzido maximizando o reuso de teste usando modelos que representam variabilidades entre os produtos. O objetivo da tese é automatizar a geração de compactos conjuntos de testes com alta capacidade de detecção de falhas e baixa redundância de teste entre produtos. Para alcançar tal objetivo, testes equivalentes são identificados para um conjunto de produtos usando conjuntos de teste completos e configuráveis. Duas direções de pesquisa são exploradas, uma centrada no produto e a outra centrada na linha de produto. Foram gerados conjuntos de teste que tenham cobertura de falhas completa a partir de máquinas de estado com e sem restrições de características. A implementação de uma ferramenta foi desenvolvida para automatizar a geração de teste. Além disso, a abordagem proposta foi avaliada usando exemplos, estudos experimentais e um estudo de caso industrial. Os resultados indicam uma redução de esforço de teste de 36% na primeira direção de pesquisa para uma linha com 24 produtos, e na segunda linha de pesquisa uma redução incremental com mais produtos a serem testados. Para 6 produtos uma redução de 15% (do estudo de caso), e para 20 produtos randomicos uma redução de 50% (dos estudos experimentais).

The deals of thesis were described methods for designing safety applications, made analysis of possible microcontroller faults of long-run system, described software and hardware methods for fault detection in microcontroller and applied some March test to microcontroller. To application were chosen MATS+, PMOVI and March SS tests. These tests were modified to word-oriented memory. Further it was made analysis of modified tests to determination fault coverage, testing times and program memory requirement. To determination of fault coverage was created virtual memory with fault function models. March tests were compared with each other and with another pattern test (checkboard test).