With advances in technology, modern integrated circuits have higher complexities and reduced transistor sizing. In deep sub-micron, the parameter variation-control is difficult and component delays vary from one manufactured chip to another. Therefore, the delays are not discrete values but are a statistical quantity, and statistical evaluation methods have gained traction. Furthermore, fault injection based gate-level fault coverage is non-scalable and statistical estimation methods are preferred. This dissertation focuses on scalable statistical methods to select critical paths in the presence of process variations, and to improve the defect coverage for complex integrated circuits. In particular, we investigate the sensitization probability of a path by a test pattern under statistical delays. Next, we investigate test pattern generation for improving the sensitization probability of a path, selecting critical paths that yield high defect coverage, and scalable method to estimate fault coverage of complex designs using machine learning techniques.

This thesis targets the problem of critical path identification in sub-micron devices. Delays are described using Probability density functions (Pdfs) in order to model the probabilistic nature of the problem. Thus, a deterministic critical path response is not possible. The probability that each path is critical is reported instead. Extensive literature review has being done and presented in detail. Heuristics for accurate critical path calculations are described and results are compared to those from Monte Carlo simulations.