In this thesis, we will investigate the degradation of the low temperature polycrystalline silicon TFTs (LTPS TFTS) under the electrical stress. The electrical stress is divided into two parts of ac stress and dc stress. We used ac stress and dc stress conditions to stress different TFTs respectively and investigate the influence of grain boundary in n-type TFT and p-type TFT by use of electrical analysis. On the other hand, degradation mechanism was confirmed by measured capacitance. In n-type TFT, the SLS poly-Si TFT which contains GB perpendicular to the channel direction owns the higher ability against dc stress and poorer ability against ac stress than the poly-Si TFT which does not contain GB. The physical mechanism for these results has been reasonably deduced by use of TFT device simulation tool (ISE_TCAD). In p-type TFT, the enhancement phenomenon is always observed after dc or ac stress. There are both existed a power-law between the variation of the drain current with stress time. The slope of power-law is related to the shortening speed of effective channel length. In either dc stress or ac stress, there are two effective factors. The one factors of them is the degradation of poly-Si film, and another one is the effective channel length shortening. In the competition of these two effective factors, the GB-TFT has more obvious enhancement than GB-TFT during dc stress. Nevertheless, during the ac stress the GB-TFT is without larger enhancement than NGB-TFT because of serious poly-Si film damage.